Operation
BANK/ROW ACTIVATION
Before any READ or WRITE commands can be issued
to a bank within the SDRAM, a row in that bank must be
“opened.” This is accomplished via the ACTIVE com-
mand, which selects both the bank and the row to be
activated (see Figure 3).
After opening a row (issuing an ACTIVE command), a
READ or WRITE command may be issued to that row,
subject to the tRCD specification. tRCD (MIN) should be
divided by the clock period and rounded up to the next
whole number to determine the earliest clock edge after
the ACTIVE command on which a READ or WRITE com-
mand can be entered. For example, a tRCD specification
of 20ns with a 125 MHz clock (8ns period) results in 2.5
clocks, rounded to 3. This is reflected in Figure 4, which
covers any case where 2 < tRCD (MIN)/tCK - 3. (The same
procedure is used to convert other specification limits
from time units to clock cycles.)
A subsequent ACTIVE command to a different row in
the same bank can only be issued after the previous
active row has been “closed” (precharged). The mini-
mum time interval between successive ACTIVE com-
mands to the same bank is defined by tRC.
A subsequent ACTIVE command to another bank can
be issued while the first bank is being accessed, which
results in a reduction of total row-access overhead. The
minimum time interval between successive ACTIVE com-
mands to different banks is defined by tRRD.
ADVANCE
512Mb: x4, x8, x16
SDRAM
CLK
CKE HIGH
CS#
RAS#
CAS#
WE#
A0-A12
ROW
ADDRESS
BA0, BA1
BANK
ADDRESS
Figure 3
Activating a Specific Row In a
Specific Bank
T0
T1
T2
T3
T4
CLK
COMMAND
ACTIVE
NOP
NOP
READ or
WRITE
tRCD
DON’T CARE
Figure 4
Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK < 3
512Mb: x4, x8, x16 SDRAM
512MSDRAM_D.p65 – Rev. D; Pub 1/02
14
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©2000, Micron Technology, Inc.