KS8995XA(2008) View Datasheet(PDF) - Micrel
Part Name
Description
Manufacturer
KS8995XA Datasheet PDF : 51 Pages
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Micrel, Inc.
KS8995XA
Pin Number
61
62
63
64
65
Pin Name
PMRXDV
PMRXD3
PMRXD2
PMRXD1
PMRXD0
Type(1)
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
66
PMRXER
Ipd/O
67
PCRS
Ipd/O
68
PCOL
Ipd/O
69
SMTXEN
Ipd
Port
5
5
5
5
5
5
5
5
Pin Function(2)
PHY[5] MII receive data valid.
PHY[5] MII receive bit 3. Strap option: PD (default) = enable flow
control; PU = disable flow control.
PHY[5] MII receive bit 2. Strap option: PD (default) = disable back
pressure; PU = enable back pressure.
PHY[5] MII receive bit 1. Strap option: PD (default) = drop excessive
collision packets; PU = does not drop excessive collision packets.
PHY[5] MII receive bit 0. Strap option: PD (default) = disable
aggressive back-off algorithm in half-duplex mode; PU = enable for
performance enhancement.
PHY[5] MII receive error. Strap option: PD (default) = packet size
1518/1522 bytes; PU = 1536 bytes.
PHY[5] MII carrier sense/strap option for port 4 only. PD (default) =
force half-duplex if auto-negotiation is disabled or fails. PU = force full-
duplex if auto negotiation is disabled or fails. Refer to Register 76.
PHY[5] MII collision detect/ strap option for port 4 only. PD (default) =
no force flow control, normal operation. PU = force flow control. Refer
to Register 66.
Switch MII transmit enable.
70
SMTXD3
Ipd
Switch MII transmit bit 3.
71
SMTXD2
Ipd
Switch MII transmit bit 2.
72
SMTXD1
Ipd
Switch MII transmit bit 1.
73
SMTXD0
Ipd
Switch MII transmit bit 0.
74
SMTXER
Ipd
Switch MII transmit error.
75
SMTXC
I/O
Switch MII transmit clock. PHY or MAC mode MII.
76
GNDD
Gnd
Digital ground.
77
VDDIO
P
3.3V digital VDD for digital I/O circuitry.
78
SMRXC
I/O
Switch MII receive clock. PHY or MAC mode MII.
79
SMRXDV
Ipd/O
80
SMRXD3
Ipd/O
81
SMRXD2
Ipd/O
82
SMRXD1
Ipd/O
83
SMRXD0
Ipd/O
Switch MII receive data valid.
Switch MII receive bit 3. Strap option: PD (default) = Disable Switch MII
full-duplex flow control; PU = Enable Switch MII full-duplex flow control.
Switch MII receive bit 2. Strap option: PD (default) = Switch MII in full-
duplex mode; PU = Switch MII in half-duplex mode.
Switch MII receive bit 1. Strap option: PD (default) = Switch MII in
100Mbps mode; PU = Switch MII in 10Mbps mode.
Switch MII receive bit 0; Strap option: see “Register 11[1].”
84
SCOL
Ipd/O
Switch MII collision detect.
85
SCRS
Ipd/O
Switch mode carrier sense.
Notes:
1. P = Power supply.
I = Input.
O = Output.
I/O = Bidirectional.
Gnd = Ground.
Ipu = Input w/internal pull-up.
Ipd = Input w/internal pull-down.
Ipd/O = Input w/internal pull-down during reset, output pin otherwise.
Ipu/O = Input w/internal pull-up during reset, output pin otherwise.
2. PU = Strap pin pull-up.
PD = Strap pull-down.
Otri = Output tristated.
September 2008
11
M9999-091508
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