6 4 C O M / 1 2 8 S E G G R A P H I C D R I V E R F O R D O T M A T RI X L C D
S6B0708
RESET
Name
RESETB
I/O Type
I
Description
Reset input
Chip is initialized when RESETB is low
LCD DRIVER OUTPUTS
Name
C1 - C64
S1 - S128
PCLK2
ADC
SHL
I/O Type
O
O
I
Description
LCD driver common output
LCD driver segment output
Phase of internal shift clock (CLK2)
PCLK2
Phase of Internal Shift Clock (CLK2)
H
Data shift at the rising edge of CLK2
L
Data shift at the falling edge of CLK2
I
Address control signal of Y address counter.
ADC
Segment Output Direction
H S1 → S2 ..... S63→ S65 → S66 ..... S127→ S128
L S64 → S63 ..... S2→ S1 → S128 → S127..... S66→ S65
I
Selection of data shift direction
SHL
Data Shift Direction
H C1 → C2 → C3 ..... C62 → C63 → C64
L C64 → C63 → C62 ..... C3 → C2 → C1
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