W9812G6GH View Datasheet(PDF) - Winbond

Part Name

Description

Manufacturer

W9812G6GH

2M X 4 BANKS X 16 BITS SDRAM

Winbond 

W9812G6GH

11. OPERATING TIMING EXAMPLE

11.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)

CLK

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23

CS

RAS

CAS

tRC

tRAS

tRC

tRP

tRAS

tRC

tRAS

tRP

tRC

tRP

tRAS

WE

BS0

BS1

A10 RAa

tRCD

A0-A9, RAa

A11

CAw

DQM

RBb

tRCD

tRCD

RAc

RBd

tRCD

RAe

RBb

CBx

RAc

CAy

RBd

CBz

RAe

CKE

DQ

Bank #0 Active

Bank #1

Bank #2

Idle

Bank #3

tRRD

tAC

aw0 aw1 aw2 aw3

tRRD

tAC

bx0 bx1 bx2 bx3

tRRD

tAC

tAC

cy0 cy1 cy2 cy3

tRRD

Read

Precharge

Active

Read

Active

Read

Precharge

Active

Precharge

Read

Active

Publication Release Date:Aug. 13, 2007

- 21

-Revision A06

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