MAX19705ETM View Datasheet(PDF) - Maxim Integrated
Part Name
Description
Manufacturer
MAX19705ETM Datasheet PDF : 37 Pages
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10-Bit, 7.5Msps, Ultra-Low-Power
Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 7.5MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN =
CCOM = 0.33µF, unless otherwise noted. CL < 5pF on all aux-DAC outputs. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
VDD Supply Current
Standby mode: CLK = 0 or OVDD;
aux-DACs ON and at midscale,
aux-ADC ON
Idle mode: fCLK = 7.5MHz; aux-DACs ON
and at midscale, aux-ADC ON
2.9
3.5
mA
4.7
6
Shutdown mode: CLK = 0 or OVDD
0.6
µA
Ext1-Rx, Ext2-Rx, Ext3-Rx, Ext4-Rx,
SPI1-Rx, SPI3-Rx states; receive ADC
operating mode (Rx): fCLK = 7.5MHz,
fIN = 1.875MHz on both channels;
aux-DACs ON and at midscale,
aux-ADC ON
1.4
mA
OVDD Supply Current
Rx ADC DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
DC Gain Matching
Offset Matching
Gain Temperature Coefficient
Power-Supply Rejection
Ext1-Tx, Ext2-Tx, Ext3-Tx, Ext4-Tx,
SPI2-Tx, SPI4-Tx states; transmit DAC
operating mode (Tx): fCLK = 7.5MHz, fOUT
69
= 620kHz on both channels; aux-DACs
ON and at midscale, aux-ADC ON
µA
Standby mode: CLK = 0 or OVDD; aux-
1
DACs ON and at midscale, aux-ADC ON
Idle mode: fCLK = 7.5MHz; aux-DACs ON
13.8
and at midscale, aux-ADC ON
Shutdown mode: CLK = 0 or OVDD
0.01
N
INL
DNL
Guaranteed no missing code (Note 2)
Residual DC offset error
Include reference error
PSRR
Offset error (VDD ±5%)
Gain error (VDD ±5%)
-1
-5.5
-8
-0.25
10
±0.6
±0.4
±0.4
±1.65
±0.01
±12
±13
±1.7
±0.05
+1
+5.5
+11
+0.25
Bits
LSB
LSB
%FS
%FS
dB
LSB
ppm/°C
LSB
%FS
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