LT3083EDF-TR View Datasheet(PDF) - Linear Technology

Part Name

Description

Manufacturer

LT3083EDF-TR

Adjustable 3A Single Resistor Low Dropout Regulator

Linear Technology 

APPLICATIONS INFORMATION

20

BOTH CAPACITORS ARE 16V,

1210 CASE SIZE, 10µF

0

X5R

–20

–40

–60

Y5V

–80

–100

0 2 4 6 8 10 12 14 16

DC BIAS VOLTAGE (V)

3083 F03

Figure 3. Ceramic Capacitor DC Bias Characteristics

40

20

0

X5R

–20

–40

Y5V

–60

–80

BOTH CAPACITORS ARE 16V,

–100 1210 CASE SIZE, 10µF

–50 –25 0 25 50 75

TEMPERATURE (°C)

100 125

3083 F04

Figure 4. Ceramic Capacitor Temperature Characteristics

VIN

4.8V

TO 20V

10µF

VIN

LT3083

VCONTROL

VIN

+

–

SET

LT3083

OUT 10mΩ

VCONTROL

+

–

SET

33k

OUT 10mΩ

VOUT

3.3V

6A

10µF

3083 F05

Figure 5. Parallel Devices

LT3083

effective value as low as 1μF to 2μF for the DC bias voltage

applied and over the operating temperature range. The X5R

and X7R dielectrics result in more stable characteristics

and are more suitable for use as the output capacitor.

The X7R type has better stability across temperature,

while the X5R is less expensive and is available in higher

values. Care still must be exercised when using X5R and

X7R capacitors. The X5R and X7R codes only specify

operating temperature range and maximum capacitance

change over temperature. Capacitance change due to DC

bias with X5R and X7R capacitors is better than Y5V and

Z5U capacitors, but can still be significant enough to drop

capacitor values below appropriate levels. Capacitor DC

bias characteristics tend to improve as component case

size increases, but expected capacitance at operating

voltage should be verified.

Voltage and temperature coefficients are not the only

sources of problems. Some ceramic capacitors have a

piezoelectric response. A piezoelectric device generates

voltage across its terminals due to mechanical stress. In a

ceramic capacitor, the stress can be induced by vibrations

in the system or thermal transients.

Paralleling Devices

Higher output current is obtained by paralleling multiple

LT3083s together. Tie the individual SET pins together and

tie the individual IN pins together. Connect the outputs in

common using small pieces of PC trace as ballast resistors

to promote equal current sharing. PC trace resistance in

mΩ/inch is shown in Table 2. Ballasting requires only a

tiny area on the PCB.

Table 2. PC Board Trace Resistance

WEIGHT (oz)

10mil WIDTH

1

54.3

2

27.1

Trace resistance is measured in mΩ/in

20mil WIDTH

27.1

13.6

The worst-case room temperature offset, only ±4mV

(DD-PAK, T Packages) between the SET pin and the OUT

pin, allows the use of very small ballast resistors.

As shown in Figure 5, each LT3083 has a small 10mΩ

ballast resistor, which at full output current gives better

than 80% equalized sharing of the current. The external

3083fa

13

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