RT8206A View Datasheet(PDF) - Richtek Technology

Part Name

Description

Manufacturer

RT8206A

High Efficiency, Main Power Supply Controllers for Notebook Computers

Richtek Technology 

RT8206A/B

BOOT1 (Pin 17)

Boost Flying Capacitor Connection for SMPS1. Connect

to an external capacitor according to the typical application

circuits.

LGATE1 (Pin 18)

SMPS1 Synchronous-Rectifier Gate drive Output. LGATE1

swings between PGND and PVCC.

PVCC (Pin 19)

PVCC is the supply voltage for the low side MOSFET

driver LGATEx. Connect a 5V power source to the PVCC

pin (bypass with 1μF MLCC capacitor to PGND if

necessary). There is an internal 10Ω connecting from

PVCC to VCC. Make sure that both VCC and PVCC are

bypassed with 1μF MLCC capacitors.

SECFB (Pin 20) (RT8206A)

The SECFB is used to monitor the optional external 14V

charge pump. Connect a resistive voltage divider from the

14V charge pump output to GND to detect the output. If

SECFB drops below the threshold voltage, LGATE1 will

be turned on for 300ns. This will refresh the external charge

pump driven by LGATE1 without over discharging the

output voltage.

NC (Pin 20) (RT8206B)

No Internal Connection.

GND [Pin 21, 33 (Exposed Pad)]

Analog Ground for both SMPS and LDO. The exposed

pad must be soldered to a large PCB and connected to

GND for maximum power dissipation.

PGND (Pin 22)

Power Ground for SMPS controller. Connect PGND

externally to the underside of the exposed pad.

LGATE2 (Pin 23)

SMPS2 Synchronous-Rectifier Gate drive Output. LGATE2

swings between PGND and PVCC.

BOOT2 (Pin 24)

Boost Flying Capacitor Connection for SMPS2. Connect

this pin to an external capacitor according to the typical

application circuits.

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6

PHASE2 (Pin 25)

Inductor Connection for SMPS2. PHASE2 is the internal

lower supply rail for the UGATE2 high side gate driver.

PHASE2 is the current sense input for the SMPS2.

UGATE2 (Pin 26)

High Side MOSFET Floating Gate Driver Output for

SMPS2. UGATE2 swings between PHASE2 and BOOT2.

EN2 (Pin 27)

SMPS2 Enable Input. The SMPS2 will be enabled if EN2

is greater than the logic high level and be disabled if EN2

is less than the logic low level. If EN2 is connected to

REF, the SMPS2 starts after the SMPS1 reaches

regulation (delay start). Drive EN2 below 0.8V to clear

fault level and reset the fault latches.

PGOOD2 (Pin 28)

SMPS2 Power Good Open-Drain Output. PGOOD2 is low

when the SMPS2 output voltage is more than 7.5% below

the normal regulation point or during soft-start. PGOOD2

is high impedance when the output is in regulation and

the soft-start circuit has terminated. PGOOD2 is low in

shutdown.

SKIP (Pin 29)

SMPS Operation Mode Control.

SKIP = GND : DEM operation

SKIP = REF : Ultrasonic Mode operation

SKIP = VCC : PWM operation.

VOUT2 (Pin 30)

SMPS2 Output Voltage Sense Input. Connect this pin to

the SMPS2 output. VOUT2 is an input to the constant

on-time-PWM one-shot circuit. It also serves as the

SMPS2 feedback input in fixed voltage mode.

ILIM2 (Pin 31)

SMPS2 Current Limit Adjustment. The GND − PHASE2

current limit threshold is 1/10th the voltage seen at ILIM2

over a 0.5V to 2V range. There is an internal 5μA current

source from VCC to ILIM2. The logic current limit threshold

is default to 100mV value if ILIM2 is higher than (VCC −

1V).

DS8206A/B-06 August 2011

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