AD5302 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD5302 Datasheet PDF : 24 Pages
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AD5302/AD5312/AD5322
TIMING CHARACTERISTICS
VDD = 2.5 V to 5.5 V, all specifications TMIN to TMAX, unless otherwise noted.1, 2, 3
Table 3.
Parameter
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
Limit at TMIN, TMAX (A, B Version)
33
13
13
0
5
4.5
0
100
20
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Conditions/Comments
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC to SCLK Active Edge Setup Time
Data Setup Time
Data Hold Time
SCLK Falling Edge to SYNC Rising Edge
Minimum SYNC High Time
LDAC Pulse Width
SCLK Falling Edge to LDAC Rising Edge
1 Guaranteed by design and characterization, not production tested.
2 All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
3 See Figure 2.
t1
SCLK
SYNC
DIN1
t8
t4
t3
t2
t7
t6
t5
DB15
DB0
t9
LDAC
t10
LDAC
1SEE INPUT SHIFT REGISTER SECTION.
Figure 2. Serial Interface Timing Diagram
Rev. D | Page 5 of 24
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