AUSTIN SEMICONDUCTOR, INC.
EARLY WRITE CYCLE
AS4LC1M16 883C
1 MEG x 16 DRAM
PRELIMINARY
tRC
tRAS
tRP
RAS VVIIHL
tCSH
tRSH
NOTE:
CASL/CASH VVIIHL
,, ,,, ,,,,, ADDR VVIIHL
,,,,,,,,,,,,, ,,,,,,,,,,,, WE VVIIHL
,,,,,,,,,,,,,,,,,,, DQ
V IOH
V IOL
, , , , ,, , OE
V IH
V IL
tCRP
tASR
tRAD
tRAH
ROW
tWRP tWRH
NOTE 1
tRCD
tCAS
tCLCH
tAR
tASC
tRAL
tCAH
tWCS
COLUMN
tCWL
tRWL
tWCR
tWCH
tWP
tACH
tDHR
tDS
tDH
VALID DATA
ROW
, ,DON’T CARE
,UNDEFINED
,, 1. Although ?W/E is a “don’t care” at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement
?W/E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
TIMING PARAMETERS
SYM
tACH
tAR
tASC
tASR
tCAH
tCAS
tCLCH
tCRP
tCSH
tCWL
tDH
tDHR
tDS
tRAD
-6
MIN MAX
15
45
0
0
10
12 10,000
10
5
50
15
10
45
0
12 30
-7
MIN MAX
15
50
0
0
12
13 10,000
10
5
55
15
12
55
0
12 35
-8
MIN MAX
20
60
0
0
15
20 10,000
10
5
60
20
15
55
0
15 40
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYM
tRAH
tRAL
tRAS
tRC
tRCD
tRP
tRSH
tRWL
tWCH
tWCR
tWCS
tWP
tWRH
tWRP
-6
MIN MAX
10
30
60 10,000
110
14 45
40
13
15
10
45
0
10
10
10
-7
MIN MAX
10
35
70 10,000
130
14 50
50
15
15
12
55
0
12
10
10
-8
MIN MAX
10
40
80 10,000
150
20 60
60
0
20
15
60
0
15
10
10
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AS4LC1M16
REV. 3/97
DS000020
2-104
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.