AS4LC1M16883C-8EC View Datasheet(PDF) - Austin Semiconductor
Part Name
Description
Manufacturer
AS4LC1M16883C-8EC Datasheet PDF : 22 Pages
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AUSTIN SEMICONDUCTOR, INC.
AS4LC1M16 883C
1 MEG x 16 DRAM
PRELIMINARY
EDO-PAGE-MODE EARLY-WRITE CYCLE
tRASP
tRP
RAS
V
V
IH
IL
tCSH
tPC
tRSH
tCRP
tRCD
tCAS, tCLCH
tCP
tCAS, tCLCH
tCP
tCAS, tCLCH
tCP
CASL/CASH
V
V
IH
IL
,,,,,, ,,,,, , , , ADDR
V
V
IH
IL
,,,,, ,,, ,,,, ,,,,, WE VVIIHL
,,,,,,,,,,,,,,,,,,,, ,,,,,, DQ
V
V
IOH
IOL
, , ,,,,,, OE VVIIHL
tASR
tRAD
tRAH
tAR
tACH
tASC
tCAH
ROW
tWRP tWRH
tWCS
COLUMN
tCWL
tWCH
tWP
NOTE 1
tWCR
tDHR
tDS
tDH
VALID DATA
tACH
tASC
tCAH
COLUMN
tWCS
tCWL
tWCH
tWP
tDS
tDH
VALID DATA
tACH
tASC
tRAL
tCAH
COLUMN
tWCS
tCWL
tWCH
tWP
tRWL
tDS
tDH
VALID DATA
ROW
DON’T CARE
UNDEFINED
, NOTE: 1. Although ?W/E is a “don’t care” at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement
?W/E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
TIMING PARAMETERS
SYM
tACH
tAR
tASC
tASR
tCAH
tCAS
tCLCH
tCP
tCRP
tCSH
tCWL
tDH
tDHR
tDS
tPC
-6
MIN MAX
15
45
0
0
10
12 10,000
10
10
5
50
15
10
45
0
25
-7
MIN MAX
15
50
0
0
12
13 10,000
10
10
5
55
15
12
55
0
30
-8
MIN MAX
20
60
0
0
15
20 10,000
10
10
5
60
20
15
55
0
40
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYM
tRAD
tRAH
tRAL
tRASP
tRCD
tRP
tRSH
tRWL
tWCH
tWCR
tWCS
tWP
tWRH
tWRP
-6
MIN MAX
12 30
10
30
60 125,000
14 45
40
13
15
10
45
0
10
10
10
-7
MIN MAX
12 35
10
35
70 125,000
14 50
50
15
15
12
55
0
12
10
10
-8
MIN MAX
15 40
10
40
80 100,000
20 60
60
15
20
15
60
0
15
10
10
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AS4LC1M16
REV. 3/97
DS000020
2-107
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
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