74LCX573(1999) View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

74LCX573
(Rev.:1999)

OCTAL D-TYPE LATCH NON INVERTING (3-STATE) WITH 5V TOLERANT INPUTS AND OUTPUTS

STMicroelectronics 

®

74LCX573

OCTAL D-TYPE LATCH NON INVERTING (3-STATE)

WITH 5V TOLERANT INPUTS AND OUTPUTS

s 5V TOLERANT INPUTS AND OUTPUTS

s HIGH SPEED: tPD = 8 ns (MAX.) at VCC = 3V

s POWER-DOWN PROTECTION ON INPUTS

AND OUTPUTS

s SYMMETRICAL OUTPUT IMPEDANCE:

|IOH| = IOL = 24 mA (MIN)

s PCI BUS LEVELS GUARANTEED AT 24mA

s BALANCED PROPAGATION DELAYS:

tPLH ≅ tPHL

s OPERATING VOLTAGE RANGE:

VCC (OPR) = 2.0V to 3.6V (1.5V Data Retention)

s PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 573

s LATCH-UP PERFORMANCE EXCEEDS 500mA

s ESD PERFORMANCE:

HBM >2000V; MM > 200V

DESCRIPTION

The LCX573 is a low voltage CMOS OCTAL

D-TYPE LATCH with 3 STATE OUTPUT NON

INVERTING fabricated with sub-micron silicon

gate and double-layer metal wiring C2MOS

technology. It is ideal for low power and high

speed 3.3V applications; it can be interfaced to

5V signal environment for both inputs and

outputs.

These 8 bit D-Type flip-flops are controlled by a

latch enable input (LE) and an output enable

PIN CONNECTION AND IEC LOGIC SYMBOLS

M

(Micro Package)

T

(TSSOP Package)

ORDER CODES :

74LCX573M

74LCX573T

input (OE).

While the LE input is held at a high level, the Q

outputs will follow the data input precisely.

When the LE is taken low, the Q outputs will be

latched precisely at the logic level of D input data.

While the (OE) input is low, the 8 outputs will be

in a normal logic state (high or low logic level)

and while high level the outputs will be in a high

impedance state.

It has same speed performance at 3.3V than 5V,

AC/ACT family, combined with a lower power

consumption.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

February 1999

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