NXP Semiconductors
74LV4053
Triple single-pole double-throw analog switch
Table 8. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 15.
Symbol Parameter
Conditions
−40 °C to +85 °C
Min Typ[1] Max
tdis
disable time
E to nYn, nZ; see Figure 14
[2]
VCC = 1.2 V
-
95
-
VCC = 2.0 V
-
34 61
VCC = 2.7 V
-
VCC = 3.0 V to 3.6 V; CL = 15 pF [3] -
VCC = 3.0 V to 3.6 V
[3]
-
26 46
17
-
20 37
VCC = 4.5 V
VCC = 6.0 V
Sn to nYn, nZ; see Figure 14
-
-
[2]
18 32
15 25
VCC = 1.2 V
-
90
-
VCC = 2.0 V
-
32 59
VCC = 2.7 V
-
VCC = 3.0 V to 3.6 V; CL = 15 pF [3] -
VCC = 3.0 V to 3.6 V
[3]
-
24 44
16
-
19 36
VCC = 4.5 V
-
17 31
VCC = 6.0 V
CPD
power dissipation CL = 50 pF; fi = 1 MHz;
capacitance
VI = GND to VCC
-
[4]
-
14 24
36
-
[1] All typical values are measured at Tamb = 25 °C.
[2] tpd is the same as tPLH and tPHL.
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
[3] Typical values are measured at nominal supply voltage (VCC = 3.3 V).
[4] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ((CL + CSW) × VCC2 × fo) where:
fi = input frequency in MHz, fo = output frequency in MHz
CL = output load capacitance in pF
CSW = maximum switch capacitance in pF;
VCC = supply voltage in Volts
N = number of inputs switching
Σ(CL × VCC2 × fo) = sum of the outputs.
−40 °C to +125 °C Unit
Min
Max
-
-
ns
-
73
ns
-
54
ns
-
-
ns
-
44
ns
-
38
ns
-
30
ns
-
-
ns
-
70
ns
-
52
ns
-
-
ns
-
42
ns
-
36
ns
-
28
ns
-
-
pF
74LV4053_4
Product data sheet
Rev. 04 — 10 August 2009
© NXP B.V. 2009. All rights reserved.
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