74LVC07A View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

Manufacturer

74LVC07A

Hex buffer with open-drain outputs

NXP Semiconductors. 

NXP Semiconductors

4. Functional diagram

74LVC07A

Hex buffer with open-drain outputs

1 1A

1Y 2

3 2A

2Y 4

5 3A

3Y 6

9 4A

4Y 8

11 5A

5Y 10

13 6A

6Y 12

mna535

Fig 1. Logic symbol

1

1A

1

2 1Y

3

2A

1

4

2Y

5

3A

1

6 3Y

9

4A

1

8

4Y

11

1

5A

10

5Y

13

6A

1

12

6Y

mna534

Fig 2. IEC logic symbol

5. Pinning information

5.1 Pinning

Y

A

GND

mna533

Fig 3. Logic diagram for one gate

74LVC07A

1A 1

1Y 2

2A 3

2Y 4

3A 5

3Y 6

GND 7

14 VCC

13 6A

12 6Y

11 5A

10 5Y

9 4A

8 4Y

001aad066

Fig 4. Pin configuration for SO14 and TSSOP14

74LVC07A

terminal 1

index area

1Y 2

2A 3

2Y 4

3A 5

3Y 6

GND(1)

13 6A

12 6Y

11 5A

10 5Y

9 4A

001aad067

Transparent top view

(1) This is not a supply pin. The substrate is attached to this

pad using conductive die attach material. There is no

electrical or mechanical requirement to solder this pad.

However, if it is soldered, the solder land should remain

floating or be connected to GND.

Fig 5. Pin configuration for DHVQFN14

74LVC07A

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 5 — 27 October 2011

© NXP B.V. 2011. All rights reserved.

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