AD5173BRM100-RL7(RevA) View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD5173BRM100-RL7
(Rev.:RevA)

256-Position One-Time Programmable Dual-Channel I2C Digital Potentiometers

Analog Devices 

6V

R1

10kΩ

APPLY FOR OTP ONLY

2.7V

C1

C2

P1

P2 1µF 1nF

P1=P2=FDV302P, NDS0610

VDD

AD5172/

AD5173

Figure 44. Isolate 6 V OTP Supply from 2.7 V Normal Operating Supply.

The 6 V supply must be removed once OTP is completed.

For users who operate their systems at 2.7 V, use of the

bidirectional low threshold P-Ch MOSFETs is recommended

for the supply’s isolation. As shown in Figure 44, this assumes

that the 2.7 V system voltage is applied first, and that the P1 and

P2 gates are pulled to ground, thus turning on P1 and

subsequently P2. As a result, VDD of the AD5172/AD5173

approaches 2.7 V. When the AD5172/AD5173 setting is found,

the factory tester applies the 6 V to VDD; the 6 V is also applied

to the gates of P1 and P2 to turn them off. The OTP command

is executed at this time to program the AD5172/AD5173; the

2.7 V source is therefore protected. Once the OTP is completed,

the tester withdraws the 6 V and the AD5172/AD5173’s setting

is fixed permanently.

AD5172/AD5173 achieves the OTP function through blowing

internal fuses. Users should always apply the 6 V one-time

program voltage requirement at the first program command.

Failure to comply with this requirement may lead to the change

of fuse structures, rendering programming inoperable.

AD5172/AD5173

Poor PCB layout introduces parasitics that may affect the fuse

programming. Therefore, it is recommended to add a 1 µF

tantalum capacitor in parallel with a 1 nF ceramic capacitor as

close as possible to the VDD pin. These capacitors help ensure

OTP programming success by providing proper current densi-

ties. This combination of capacitor values provides both a fast

response for high frequency transients and a larger supply of

current for extended spikes. Typically, C1 minimizes any

transient disturbances and low frequency ripple, while C2

reduces high frequency noise.

LAYOUT CONSIDERATIONS

It is a good practice to employ compact, minimum lead length

layout design. The leads to the inputs should be as direct as

possible with a minimum conductor length. Ground paths

should have low resistance and low inductance.

Note that the digital ground should also be joined remotely to

the analog ground at one point to minimize the ground bounce.

VDD

C1 + C2

1µF 1nF

VDD

AD5172

GND

Figure 45. Power Supply Bypassing

Rev. A | Page 15 of 24

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