AD5253BRUZ10 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD5253BRUZ10 Datasheet PDF : 32 Pages
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AD5253/AD5254
INTERFACE TIMING CHARACTERISTICS
All input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching
characteristics are measured using both VDD = 3 V and 5 V.
Table 3.
Parameter1
INTERFACE TIMING
SCL Clock Frequency
tBUF Bus-Free Time Between Stop and Start
tHD;STA Hold Time (Repeated Start)
tLOW Low Period of SCL Clock
tHIGH High Period of SCL Clock
tSU;STA Set-up Time for Start Condition
tHD;DAT Data Hold Time
tSU;DAT Data Set-up Time
tF Fall Time of Both SDA and SCL Signals
tR Rise Time of Both SDA and SCL Signals
tSU;STO Set-up Time for Stop Condition
EEMEM Data Storing Time
EEMEM Data Restoring Time at Power-On3
EEMEM Data Restoring Time upon Restore
Command or Reset Operation3
EEMEM Data Rewritable Time4
FLASH/EE MEMORY RELIABILITY
Endurance5
Data Retention6, 7
Symbol
Conditions
fSCL
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
tEEMEM_STORE
tEEMEM_RESTORE1
tEEMEM_RESTORE2
After this period, the first clock pulse is
generated.
VDD rise time dependent. Measure without
decoupling capacitors at VDD and VSS.
VDD = 5 V.
tEEMEM_REWRITE
Min Typ2 Max Unit
400 kHz
1.3
μs
0.6
μs
1.3
μs
0.6
μs
0.6
μs
0
0.9 μs
100
ns
300 ns
300 ns
0.6
μs
26
ms
300
μs
300
μs
540
μs
100
100
K cycles
Years
1 See Figure 23 for location of measured values.
2 Typical values represent average readings at 25°C and VDD = 5 V.
3 During power-up, all outputs are preset to midscale before restoring the EEMEM contents. RDAC0 has the shortest EEMEM restore time, whereas RDAC3 has the longest.
4 Delay time after power-on or reset before new EEMEM data to be written.
5 Endurance is qualified to 100,000 cycles per JEDEC Std. 22 Method A117 and measured at –40°C, +25°C, and +85°C; typical endurance at +25°C is 700,000 cycles.
6 Retention lifetime equivalent at junction temperature TJ = 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV derates
with junction temperature.
7 When the part is not in operation, the SDA and SCL pins should be pulled high. When these pins are pulled low, the I2C interface at these pins conducts a current of
about 0.8 mA at VDD = 5.5 V and 0.2 mA at VDD = 2.7 V.
Rev. B | Page 7 of 32
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