SPI-COMPATIBLE DIGITAL INTERFACE (DIS = 0)
SERIAL DATA-WORD FORMAT
MSB
Addr
Data
B9
B8
B7
B6
A1
A0
D7
D6
29
27
B5
B4
D5
D4
B3
B2
D3
D2
1
SDI 0
1
CLK 0
1
CS 0
1
VOUT 0
A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
RDAC REGISTER LOAD
Figure 40. AD5263 Timing Diagram (VA = 5 V, VBB = 0 V, VW = VOUT)
AD5263
LSB
B1
B0
D1
D0
20
1
SDI
(DATA IN)
0
1
CLK
0
1
CS
0
tCSHO
Dx
tCSS
VOUTVDD
0
Dx
tDS
tCH
tCH
tCL
tCS1
tCSH1
tC-SW
tS
Figure 41. Detailed SPI Timing Diagram (VA = 5 V, VBB = 0 V, VW = V ) OUT
±LSB
Rev. A | Page 15 of 28