AD5420 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD5420 Datasheet PDF : 32 Pages
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Data Sheet
Single-Channel, 12-/16-Bit, Serial Input, 4 mA to 20 mA,
Current Source DAC, HART Connectivity
AD5410/AD5420
FEATURES
12-/16-bit resolution and monotonicity
Current output ranges: 4 mA to 20 mA, 0 mA to 20 mA, or
0 mA to 24 mA
±0.01% FSR typical total unadjusted error (TUE)
±3 ppm/°C typical output drift
Flexible serial digital interface
On-chip output fault detection
On-chip reference (10 ppm/°C maximum)
Feedback/monitoring of output current
Asynchronous clear function
Power supply (AVDD) range
10.8 V to 40 V; AD5410AREZ/AD5420AREZ
10.8 V to 60 V; AD5410ACPZ/AD5420ACPZ
Output loop compliance to AVDD − 2.5 V
Temperature range: −40°C to +85°C
24-lead TSSOP and 40-lead LFCSP packages
APPLICATIONS
Process control
Actuator control
PLC
HART network connectivity
GENERAL DESCRIPTION
The AD5410/AD5420 are low cost, precision, fully integrated
12-/16-bit converters offering a programmable current source
output designed to meet the requirements of industrial process
control applications. The output current range is programmable
at 4 mA to 20 mA, 0 mA to 20 mA, or an overrange function of
0 mA to 24 mA. The output is open-circuit protected. The device
operates with a power supply (AVDD) range from 10.8 V to
60 V. Output loop compliance is 0 V to AVDD − 2.5 V.
The flexible serial interface is SPI, MICROWIRE™, QSPI™, and
DSP compatible and can be operated in 3-wire mode to mini-
mize the digital isolation required in isolated applications.
The device also includes a power-on reset function, ensuring
that the device powers up in a known state, and an asynchronous
CLEAR pin that sets the output to the low end of the selected
current range.
The total unadjusted error is typically ±0.01% FSR.
COMPANION PRODUCTS
HART Modem: AD5700, AD5700-1
DVCC
SELECT
FUNCTIONAL BLOCK DIAGRAM
DVCC
CAP1
CAP2
AV DD
CLEAR
AD5410/AD5420
R3SENSE
R2
R3
BOOST
LATCH
SCLK
SDIN
SDO
INPUT SHIFT
REGISTER
AND CONTROL
LOGIC
12/16
12-/16-BIT
DAC
POWER-
ON
RESET
VREF
RSET
IOUT
FAULT
RSET
REFOUT REFIN
Figure 1.
GND
Rev. F
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