AD713AQ View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD713AQ Datasheet PDF : 21 Pages
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loop gain. At high frequencies, where the loop gain is low, the
amplifier output impedance can approach its open-loop value.
1 VLOGIC
STS 28
2 12/8 (MSB) DB11 27
3 CS
DB10 26
AD574A
TOP VIEW
(Not to Scale)
4 AO
5 R/C
6 CE
DB9 25
DB8 24
DB7 23
7 VCC
DB6 22
GAIN ADJUST
8 REF OUT
9 AC
DB5 21
DB4 20
+15V
0.1µF
R2 100Ω
R1 100Ω
10 REF IN
11 VEE
12 BIP OFF
DB3 19
DB2 18
DB1 17
4
OFFSET ADJUST 13 10VIN
±10V
14 20VIN
ANALOG
INPUT
1/4
11 0.1µF
ANALOG COM
AD713
–15V
(LSB) DB0 16
DC 15
Figure 37. AD713 as an ADC Buffer
HIGH
BITS
MIDDLE
BITS
LOW
BITS
Most IC amplifiers exhibit a minimum open-loop output imped-
ance of 25 Ω, due to current limiting resistors. A few hundred
microamps reflected from the change in converter loading can
introduce errors in instantaneous input voltage. If the analog-
to-digital conversion speed is not excessive and the bandwidth
of the amplifier is sufficient, the amplifier output returns to
the nominal value before the converter makes its comparison.
However, many amplifiers have relatively narrow bandwidths,
yielding slow recovery from output transients. The AD713 is
ideally suited as a driver for ADCs because it offers both a wide
bandwidth and a high open-loop gain.
1mV
AD713 BUFF
100 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •
90
10
0% • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •
500mV
10V ADC IN
200ns
Figure 38. Buffer Recovery Time Source Current = 2 mA
AD713
1mV
AD713 BUFF
100 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •
90
10
0% • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •
500mV
–5V ADC IN
200ns
Figure 39. Buffer Recovery Time Sink Current = 1 mA
Driving A Large Capacitive Load
The circuit of Figure 40 uses a 100 Ω isolation resistor that
enables the amplifier to drive capacitive loads exceeding
1500 pF; the resistor effectively isolates the high frequency
feedback from the load and stabilizes the circuit. Low frequency
feedback is returned to the amplifier summing junction via the
low-pass filter formed by the 100 Ω series resistor and the load
capacitance, CL. Figure 41 shows a typical transient response for
this connection.
4.99kΩ
30pF
4.99kΩ
INPUT
TYPICAL CAPACITANCE
LIMIT FOR VARIOUS
LOAD RESISTORS
+VS
0.1µF
4
1/4
AD713
11 0.1µF
100Ω
OUTPUT
CL RL
RL CL UP TO
2kΩ 1500pF
10kΩ 1500pF
–VS
20kΩ 1000pF
Figure 40. Circuit for Driving a Large Capacitance Load
5V
1µs
100 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •
90
10
0% • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •
Figure 41. Transient Response, RL = 2 kΩ, CL = 500 pF
Rev. F | Page 13 of 20
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