AD9265(RevA) View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD9265 Datasheet PDF : 44 Pages
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AD9265
SWITCHING SPECIFICATIONS
−1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted.
Table 4.
Parameter
CLOCK INPUT PARAMETERS
Input Clock Rate
Conversion Rate2
DCS Enabled
DCS Disabled
CLK Period—Divide-by-1 Mode (tCLK)
CLK Pulse Width High (tCH)
Divide-by-1 Mode, DCS Enabled
Divide-by-1 Mode, DCS Disabled
Divide-by-3 Mode, Divide-by-5 Mode, and
Divide-by-7 Mode, DCS Enabled3
Divide-by-2 Mode, Divide-by-4 Mode, Divide-
by-6 Mode and Divide-by-8 Mode, DCS
Enabled or DCS Disabled3
Aperture Delay(tA)
Aperture Uncertainty (Jitter, tJ)
DATA OUTPUT PARAMETERS
CMOS Mode
Data Propagation Delay (tPD)
DCO Propagation Delay (tDCO)4
DCO to Data Skew (tSKEW)
Pipeline Delay (Latency)
LVDS Mode
Data Propagation Delay (tPD)
DCO Propagation Delay (tDCO)4
DCO to Data Skew (tSKEW)
Pipeline Delay (Latency)
Wake-Up Time5
OUT-OF-RANGE RECOVERY TIME
AD9265BCPZ-801 AD9265BCPZ-1051
Temp Min Typ Max Min Typ Max
Full
625
625
Full 20
80 20
105
Full 10
80 10
105
Full 12.5
9.5
Full 3.75 6.25 8.75 2.85 4.75 6.65
5.9 6.25 6.6 4.5 4.75 5.0
Full 0.8
0.8
Full 0.8
0.8
Full
1.0
1.0
Full
0.07
0.07
Full 2.4 2.8 3.4 2.4 2.8 3.4
Full 2.7 3.4 4.2 2.7 3.4 4.2
Full 0.3 0.6 0.9 0.3 0.6 0.9
Full
12
12
Full 2.6 3.4 4.2 2.6 3.4 4.2
Full 3.3 3.8 4.3 3.3 3.8 4.3
Full −0.3 0.4 1.2 −0.3 0.4 1.2
Full
12.5
12.5
Full
500
500
Full
2
2
AD9265BCPZ-1251
Min Typ Max
625
20
125
10
125
8
2.4 4 5.6
3.8 4 4.2
0.8
0.8
1.0
0.07
2.4 2.8 3.4
2.7 3.4 4.2
0.3 0.6 0.9
12
2.6 3.4 4.2
3.3 3.8 4.3
−0.3 0.4 1.2
12.5
500
2
Unit
MHz
MSPS
MSPS
ns
ns
ns
ns
ns
ns
ps rms
ns
ns
ns
Cycles
ns
ns
ns
Cycles
μs
Cycles
1 The suffix following the part number refers to the model found in the Ordering Guide section.
2 Conversion rate is the clock rate after the divider.
3 See the Input Clock Divider section for additional information on using the DCS with the input clock divider.
4 Additional DCO delay can be added by writing to Bit 0 through Bit 4 in SPI Register 0x17 (see Table 17).
5 Wake-up time is defined as the time required to return to normal operation from power-down mode.
Rev. A | Page 8 of 44
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