AD9572ACPZPEC-R7(Rev0) View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD9572ACPZPEC-R7
(Rev.:Rev0)

Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs

Analog Devices 

AD9572

Parameter

Min

PLL Noise (125 MHz LVPECL Output)

@ 1 kHz

@ 10 kHz

@ 100 kHz

@ 1 MHz

@ 10 MHz

@ 30 MHz

PLL Noise (100 MHz LVPECL Output)

@ 1 kHz

@ 10 kHz

@ 100 kHz

@ 1 MHz

@ 10 MHz

@ 30 MHz

Phase Noise (33.33 MHz CMOS Output)

@ 1 kHz

@ 10 kHz

@ 100 kHz

@ 1 MHz

@ 5 MHz

Phase Noise (25 MHz CMOS Output)

@ 1 kHz

@ 10 kHz

@ 100 kHz

@ 1 MHz

@ 5 MHz

Spurious Content1

PLL Figures of Merit

Typ

Max

Unit

Test Conditions/Comments

−122

−127

−128

−148

−152

−153

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

33.33 MHz output disabled

33.33 MHz output disabled

33.33 MHz output disabled

33.33 MHz output disabled

33.33 MHz output disabled

33.33 MHz output disabled

−122

−128

−130

−148

−150

−151

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

33.33 MHz output disabled

33.33 MHz output disabled

33.33 MHz output disabled

33.33 MHz output disabled

33.33 MHz output disabled

33.33 MHz output disabled

−130

−138

−139

−152

−152

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

−133

−142

−148

−148

−148

−70

−217.5

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

dBc

dBc/Hz

Dominant amplitude with all outputs active

1 When the 33.33 MHz, 100 MHz, and 125 MHz clocks are enabled simultaneously, a worst-case −50 dBc spurious content might be presented on Pin 21 and Pin 22 only.

LVDS CLOCK OUTPUT JITTER

Typical (typ) is given for VS = 3.3 V, TA = 25°C, unless otherwise noted.

Table 2.

Jitter Integration

Bandwidth (Typ)

12 kHz to 20 MHz

1.875 MHz to

20 MHz

637 kHz to 10 MHz

200 kHz to 10 MHz

12 kHz to 35 MHz

100 MHz

33M = Off/On

508/490

316/308

106.25 MHz 125 MHz

156.25 MHz

33M = Off/On 33M = Off/On 33M = Off/On

402/440

418/883

417/423

178/185

167/217

253/776

500 (off only)

Unit

fS rms

fS rms

fS rms

fS rms

fS rms

Test Conditions/Comments

LVDS output frequency combinations

are 1 × 156.25 MHz, 1 × 100 MHz, 1 ×

125 MHz, 2 × 106.25 MHz

LVDS output frequency combinations

are 1 × 156.25 MHz, 1 × 100 MHz, 1 ×

125 MHz, 2 × 106.25 MHz

LVDS output frequency combinations

are 1 × 156.25 MHz, 1 × 100 MHz, 1 ×

125 MHz, 2 × 106.25 MHz

LVDS output frequency combinations

are 1 × 156.25 MHz, 1 × 100 MHz, 1 ×

125 MHz, 2 × 106.25 MHz

LVDS output frequency combinations

are 1 × 156.25 MHz, 2 × 125 MHz, 2 ×

106.25 MHz

Rev. 0 | Page 4 of 20

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