Pin No.
1
2
3
4, 22
5, 21
6
7–18
19–20, 35–36
23–34
37, 38
39
40
41
42
43
44
45
46
47
48
Mnemonic
RESET
CLK+
CLK–
DCOM
DVDD
PLLLOCK
P1B11–P1B0
Reserved
P2B11–P2B0
DIV0, DIV1
REFIO
FSADJ
AVDD
IOUTB
IOUTA
ACOM
CLKCOM
LPF
PLLVDD
CLKVDD
AD9753
PIN FUNCTION DESCRIPTIONS
Description
Internal Clock Divider Reset
Differential Clock Input
Differential Clock Input
Digital Common
Digital Supply Voltage
PLL Lock Indicator Output
Data Bits DB11 to DB0, Port 1
Data Bits DB11 to DB0, Port 2
Control inputs for PLL and input port selector mode, see Tables I and II for details.
Reference Input/Output
Full-Scale Current Output Adjust
Analog Supply Voltage
Differential DAC Current Output
Differential DAC Current Output
Analog Common
Clock and Phase-Locked Loop Common
PLL Loop Filter
Phase-Locked Loop Supply Voltage
Clock Supply Voltage
PIN CONFIGURATION
48 47 46 45 44 43 42 41 40 39 38 37
RESET 1
CLK+ 2
CLK– 3
DCOM 4
DVDD 5
PLLLOCK 6
MSB–P1B11 7
P1B10 8
P1B9 9
P1B8 10
P1B7 11
P1B6 12
PIN 1
IDENTIFIER
AD9753
TOP VIEW
(Not to Scale)
36 RESERVED
35 RESERVED
34 P2B0–LSB
33 P2B1
32 P2B2
31 P2B3
30 P2B4
29 P2B5
28 P2B6
27 P2B7
26 P2B8
25 P2B9
13 14 15 16 17 18 19 20 21 22 23 24
RESERVED = NO
USER CONNECTIONS
REV. 0
–5–