AD9869BCPZRL View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD9869BCPZRL Datasheet PDF : 36 Pages
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AD9869
TxPGA CONTROL
The AD9869 also contains a digital PGA in the Tx path distri-
buted between the TxDAC and IAMP. The TxPGA is used to
control the peak current from the TxDAC and IAMP over a
7.5 dB and 19.5 dB span, respectively, with 0.5 dB resolution.
A 6-bit word is used to set the TxPGA attenuation according to
the mapping shown in Figure 17. The TxDAC gain mapping is
applicable only when Bit 0 of Register 0x0E is set, and only
when the 4 LSBs of the 6-bit gain word are relevant.
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
–11
–12
–13
–14
–15
–16
–17
–18
–19
–20
0
TxDACs IOUTP OUTPUT
HAS 7.5dB RANGE
IAMPs IOUTN OUTPUT
HAS 19.5dB RANGE
8
16
24
32
40
48
56
64
6-BIT DIGITAL CODE (Decimal Equivalent)
Figure 17. Digital Gain Mapping of TxPGA
The TxPGA register can be updated via the PGA[5:0] port or
SPI port. The first method should be considered for fast updates
of the TxPGA register. Its operation is similar to the description
in the RxPGA Control section. The SPI port allows direct
update and readback of the TxPGA register via Register 0x0A
with an update rate limited to 1.6 MSPS (SCLK = 32 MHz).
Bit 6 of Register 0x0A must be set for a read or write operation.
Table 16 lists the SPI registers pertaining to the TxPGA. The
TxPGA control register default setting is for minimum attenua-
tion (0 dBFS) with the PGA[5:0] port disabled for Tx gain control.
Table 16. SPI Registers TxPGA Control
Address (Hex) Bit Description
0x0A
6
Enable TxPGA update via SPI.
5:0 TxPGA gain code.
0x0B
6
Select TxPGA via PGA[5:0].
5
Select RxPGA via PGA[5:0].
0x0E
0
TxDAC output (IAMP disabled).
Rev. 0 | Page 20 of 36
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