Data Sheet
ADF4151
LOW
NOISE AND
LOW SPUR
MODES
MUXOUT
10-BIT R COUNTER
DBR
CHARGE
PUMP
CURRENT
SETTING
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 L2 L1 M3 M2 M1 RD2 RD1 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 0 CP4 CP3 CP2 CP1 U6 U5 U4 U3 U2 U1 C3(0) C2(1) C1(0)
L1 L2 NOISE MODE
0 0 LOW NOISE MODE
0 1 RESERVED
1 0 RESERVED
1 1 LOW SPUR MODE
RD2
REFERENCE
DOUBLER
0
DISABLED
1
ENABLED
RD1 REFERENCE DIVIDE BY 2
0
DISABLED
1
ENABLED
R10 R9
0
0
0
0
.
.
.
.
.
.
1
1
1
1
1
1
1
1
.......... R2 R1 R DIVIDER (R)
.......... 0
.......... 1
.......... .
.......... .
.......... .
.......... 0
.......... 0
11
02
..
..
..
0 1020
1 1021
.......... 1
.......... 1
0 1022
1 1023
M3 M2 M1 OUTPUT
0
0
0
THREE-STATE OUTPUT
0
0
1
DVDD
0
1
0
DGND
0
1
1
R DIVIDER OUTPUT
1
0
0
N DIVIDER OUTPUT
1
0
1
ANALOG LOCK DETECT
1
1
0
DIGITAL LOCK DETECT
1
1
1
RESERVED
CP4 CP3 CP2 CP1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Figure 21. Register 2 (R2)
U6 LDF
0
FRAC-N
1
INT-N
ICP (mA)
5.1kΩ
0.28
0.56
0.84
1.13
1.41
1.69
1.97
2.25
2.53
2.81
3.09
3.38
3.66
3.94
4.22
4.5
U5 LDP
0
10ns
1
6ns
U4 PD POLARITY
0
NEGATIVE
1
POSITIVE
U1
COUNTER
RESET
0 DISABLED
1 ENABLED
U2
CP
THREE-STATE
0 DISABLED
1 ENABLED
U3 POWER-DOWN
0
DISABLED
1
ENABLED
Rev. B | Page 15 of 28