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ADMCF326 View Datasheet(PDF) - Analog Devices

Part Name
Description
Manufacturer
ADMCF326 Datasheet PDF : 36 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
a
28-Lead Flash Memory
DSP Motor Controller
ADMCF326
TARGET APPLICATIONS
Washing Machines, Refrigerator Compressors, Fans,
Pumps, Industrial Variable Speed Drives
MOTOR TYPES
AC Induction Motors
Permanent Magnet Synchronous Motors (PMSM)
Brushless DC Motors (BDCM)
FEATURES
20 MIPS Fixed-Point DSP Core
Single Cycle Instruction Execution (50 ns)
ADSP-21xx Family Code Compatible
Independent Computational Units
ALU
Multiplier/Accumulator
Barrel Shifter
Multifunction Instructions
Single Cycle Context Switch
Powerful Program Sequencer
Zero Overhead Looping
Conditional Instruction Execution
Two Independent Data Address Generators
Memory Configuration
512 ؋ 24-Bit Program Memory RAM
512 ؋ 16-Bit Data Memory RAM
4K ؋ 24-Bit Program Memory ROM
4K ؋ 24-Bit Program Flash Memory
Three Independent Programmable Sectors
Security Lock Bit
10K Erase/Program Cycles
Three-Phase 16-Bit PWM Generator
16-Bit Center-Based PWM Generator
Programmable Dead Time and Narrow Pulse Deletion
Edge Resolution to 50 ns
150 Hz Minimum Switching Frequency
Double/Single Duty Cycle Update Mode Control
Programmable PWM Pulsewidth
Special Crossover Function for Brushless DC Motors
Individual Enable and Disable for Each PWM Output
High Frequency Chopping Mode for Transformer
Coupled Gate Drives
External PWMTRIP Pin
Integrated ADC Subsystem
Six Analog Inputs
Acquisition Synchronized to PWM Switching Frequency
Internal Voltage Reference
9-Pin Digital I/O Port
Bit Configurable as Input or Output
Change of State Interrupt Support
Two 8-Bit Auxiliary PWM Timers
Synthesized Analog Output
Programmable Frequency
0% to 100% Duty Cycle
Two Programmable Operational Modes
Independent Mode/Offset Mode
16-Bit Watchdog Timer
Programmable 16-Bit Internal Timer with Prescaler
Double Buffered Synchronous Serial Port
Hardware Support for UART Emulation
Integrated Power-On Reset Function Options
28-Lead SOIC and PDIP Packages Available
ADSP-2100 BASE
ARCHITECTURE
DATA
ADDRESS
GENERATORS
DAG 1 DAG 2
PROGRAM
SEQUENCER
FUNCTIONAL BLOCK DIAGRAM
MEMORY BLOCK
PROGRAM PROGRAM
ROM
FLASH
4K ؋ 24
4K ؋ 24
PROGRAM DATA
RAM
MEMORY
512 ؋ 24 512 ؋ 16
VREF
2.5V
6
ANALOG
INPUTS
16-BIT
THREE-
PHASE
PWM
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
ARITHMETIC UNITS
ALU MAC SHIFTER
POR
TIMER
SERIAL PORT
SPORT 1
9-BIT
PIO
2 ؋ 8-BIT WATCH-
AUX
DOG
PWM
TIMER
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002

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