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ADP3196 View Datasheet(PDF) - ON Semiconductor

Part Name
Description
Manufacturer
ADP3196 Datasheet PDF : 18 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ADP3196
Pin No.
18
19
20
21
22 to 25
26, 32,
33, 40
27 to 30
31
34 to 39
Mnemonic
GND
OD
IREF
IMON
SW4 to SW1
NC
Description
Ground. All internal biasing and the logic output signals of the device are referenced to this ground.
Output Disable Logic Output. This pin is actively pulled low when the ADP3196 EN input is low or when VCC is
below its UVLO threshold to signal to the driver IC that the driver high-side and low-side outputs should go low.
Current Reference Input. An external resistor from this pin to ground sets the reference current for IFB, IDELAY, ISS,
IILIMIT and ITTSENSE.
Analog Output. Represents total load current.
Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases
should be left open.
No Connection.
PWM4 to
PMW1
VCC
VID5 to VID0
Logic Level PWM Outputs. Each output is connected to the input of an external MOSFET driver, such as the
ADP3120A. Connecting the PWM3 and/or PWM4 outputs to the ADP3196 VCC pin causes that phase to turn off,
allowing the ADP3196 to operate as a 2-, 3-, or 4-phase controller.
A 340 Ω resistor should be placed between the 12 V system supply and the VCC pin. The internal shunt
regulator maintains VCC = 5 V.
Voltage Code DAC Inputs. These six pins are pulled down to GND, providing a logic zero if left open. When in normal
operation mode, the DAC output programs the FB regulation voltage from 0.3750 V and 1.55 V (see Table 4).
Rev. 1 | Page 8 of 18 | www.onsemi.com

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