ADT7486A(2012) View Datasheet(PDF) - ON Semiconductor
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ADT7486A Datasheet PDF : 14 Pages
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ADT7484A/ADT7486A
Table 5. ELECTRICAL CHARACTERISTICS (continued)
(TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted)
Parameter
SST Timing
Conditions
Min
Bitwise Period, tBIT
High Level Time for Logic 1, tH1
(Note 2)
tBIT Defined in Speed Negotiation
0.495
0.6 tBIT
High Level Time for Logic 0, tH0
(Note 2)
0.2 tBIT
Time to Assert SST High for
Logic 1, tSU, HIGH
Hold Time, tHOLD (Note 3)
Stop Time, tSTOP
See SST Specification Rev 1.0
Device Responding to a Constant Low Level
Driven by Originator
−
−
1.25 tBIT
Time to Respond After a Reset,
−
tRESET
Response Time to Speed
Time after Powerup when Device Can
−
Negotiation After Powerup
Participate in Speed Negotiation
1. Guaranteed by design, not production tested.
2. Minimum and maximum bit times are relative to tBIT defined in the timing negotiation pulse.
3. Devices compatible with hold time specification as driven by SST originator.
Typ
−
0.75 tBIT
0.25 tBIT
−
−
2 tBIT
−
500
Max
Unit
500
ms
0.8 tBIT
ms
0.4 tBIT
ms
0.2 tBIT
ms
0.5 tBIT−M
ms
2 tBIT
ms
0.4
ms
−
ms
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