PDM4M4050 View Datasheet(PDF) - Paradigm Technology

Part Name

Description

Manufacturer

PDM4M4050

256K x 32 BiCMOS/CMOS Static RAM Module

Paradigm Technology 

Pin Configuration(1)

PD0

I/O0

I/O1

I/O2

I/O3

Vcc

A7

A8

A9

I/O4

I/O5

I/O6

I/O7

WE

A14

CS1

CS3

A16

Vss

I/O16

I/O17

I/O18

I/O19

A10

A11

A12

A13

I/O20

I/O21

I/O22

I/O23

Vss

2

1

4

3

6

5

8

7

10

9

12

11

14

13

16

15

18

17

20

19

22

21

24

23

26

25

28

27

30

29

32

31

ZIP, SIMM

34 TOP VIEW 33

36

35

38

37

40

39

42

41

44

43

46

45

48

47

50

49

52

51

54

53

56

55

58

57

60

59

62

61

64

63

Vss

PD1

I/O8

I/O9

I/O10

I/O11

A0

A1

A2

I/O12

I/O13

I/O14

I/O15

Vss

A15

CS2

CS4

A17

OE

I/O24

I/O25

I/O26

I/O27

A3

A4

A5

Vcc

A6

I/O28

I/O29

I/O30

I/O31

PD0 - Vss

PD1 - Vss

NOTE:

1. Pins 2 and 3 (PD0 and PD1) are read by the

user to determine the density of the module.

If PD0 reads VSS and PD1 reads VSS then

the module has a 256K depth.

PDM4M4050

Pin Assignment

Pin

I/O31-I/O0

A17-A0

CS4-CS1

WE

OE

PD1-PD0

VCC

VSS

Signal

Data Inputs/Outputs

Addresses

Chip Selects

Write Enable

Output Enable

Depth Identification

Power

Ground

8-46

Rev 2.2 - 7/17/97

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