AS7C33128PFD32A-166TQC View Datasheet(PDF) - Alliance Semiconductor

Part Name

Description

Manufacturer

AS7C33128PFD32A-166TQC

3.3V 128K × 32/36 pipeline burst synchronous SRAM

Alliance Semiconductor 

Timing waveform of read cycle

CLK

ADSP

ADSC

Address

GWE, BWE

CE0, CE2

tCH

tADSPS

tADSPH

tADSCS

tADSCH

tAS

tAH

A1

A2

tWS

tWH

tCSS

tCSH

®

tCYC

tCL

AS7C33128PFD32A

AS7C33128PFD36A

LOAD NEW ADDRESS

A3

CE1

tADVS

tADVH

ADV

OE

DOUT

(pipelined mode) tOE

tLZOE

DOUT

(flow-through mode)

Q(A1)

Q(A1)

tHZOE

tOH

Q(A2)

tCD

ADV INSERTS WAIT STATES

tHZC

Q(A2Ý01)

Q(A2Ý10)

Q(A2Ý11) Q(A3) Q(A3Ý01) Q(A3Ý10) Q(A3Ý11)

Q(A2Ý01)

Q(A2Ý10)

Q(A2Ý11) Q(A3) Q(A3Ý01) Q(A3Ý10) Q(A3Ý11)

tHZC

Note: Ý = XOR when MODE = HIGH/No Connect; Ý = ADD when MODE = LOW.

BW[a:d] is don’t care.

Key to switching waveform

Rising input

Falling input

Undefined/don’t care

3/22/01; v.1.0

Alliance Semiconductor

P. 7 of 11

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