Figure 5-2. Some Single Cell Modes
A
B
C
DQ
D
Q (Registered)
and/or
Q
Synthesis Mode. This mode is particularly important
for the use of VHDL/Verilog design. VHDL/Verilog
Synthesis tools generally will produce as their output
large amounts of random logic functions. Having a
4-input LUT structure gives efficient random logic
optimization without the delays associated with
larger LUT structures. The output of any cell may be
registered, tri-stated and/or fed back into a core cell.
SUM
Arithmetic Mode. Frequently used in many designs.
or
As can be seen in the figure, the AT40KAL core cell
A
B
can implement a 1-bit full adder (2-input adder with
DQ
SUM (Registered) both Carry In and Carry Out) in one core cell. Note
C
and/or
that the sum output in this diagram is registered. This
output could then be tri-stated and/or fed back into
CARRY
the cell.
A
B
C
D
CARRY IN
DQ
PRODUCT
(Registered) or
DSP/Multiplier Mode. This mode is used to
efficiently implement array multipliers. An array
PRODUCT
multiplier is an array of bitwise multipliers, each
implemented as a full adder with an upstream AND
and/or
gate. Using this AND gate and the diagonal
CARRY
interconnects between cells, the array multiplier
structure fits very well into the AT40KAL architecture.
Counter Mode. Counters are fundamental to almost
all digital designs. They are the basis of state
DQ
Q
machines, timing chains and clock dividers. A
counter is essentially an increment by one function
(i.e., an adder), with the input being an output (or a
and/or
decode of an output) from the previous stage. A 1-bit
counter can be implemented in one core cell. Again,
CARRY
the output can be registered, tri-stated and/or fed
back.
A
Tri-state/Mux Mode. This mode is used in many
B
Q
telecommunications applications, where data needs
C
to be routed through more than one possible path.
The output of the core cell is very often tri-statable
EN
for many inputs to many outputs data switching.
10 AT40KAL Series FPGA [Datasheet]
Atmel-2818G-FPGA-AT40KAL-Series-Datasheet_092013