AT40K05AL View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

AT40K05AL

5K – 50K Gates Coprocessor FPGA with FreeRAM™

Atmel Corporation 

1.3 Cache Logic Design

The AT40KAL, AT6000, and FPSLIC families are capable of implementing Cache Logic (dynamic full/partial logic

reconfiguration, without loss of data, on-the-fly) for building adaptive logic and systems. As new logic functions are

required, they can be loaded into the logic cache without losing the data already there or disrupting the operation of

the rest of the chip; replacing or complementing the active logic. The AT40KAL can act as a reconfigurable

coprocessor.

1.4 Automatic Component Generators

The AT40KAL FPGA family is capable of implementing user-defined, automatically generated, macros in multiple

designs; speed and functionality are unaffected by the macro orientation or density of the target device. This

enables the fastest, most predictable and efficient FPGA design approach, and minimizes design risk by reusing

already proven functions. The Automatic Component Generators work seamlessly with industry standard

schematic and synthesis tools to create the fastest, most efficient designs available.

The patented AT40KAL series architecture employs a symmetrical grid of small yet powerful cells connected to a

flexible busing network. Independently controlled clocks and resets govern every column of cells. The array is

surrounded by programmable I/O.

Devices range in size from 5,000 to 50,000 usable gates in the family, and have 256 to 3,048 registers. Pin

locations are consistent throughout the AT40KAL series for easy design migration in the same package footprint.

The AT40KAL series FPGAs utilize a reliable 0.35μ triple-metal, CMOS process and are 100% factory-tested. The

Atmel PC- based integrated development system (IDS) is used to create AT40KAL series designs. Multiple design

entry methods are supported.

The Atmel architecture was developed to provide the highest levels of performance, functional density, and design

flexibility in an FPGA. The cells in the Atmel array are small, efficient, and can implement any pair of Boolean

functions of (the same) three inputs or any single Boolean function of four inputs. The cell’s small size leads to

arrays with large numbers of cells, greatly multiplying the functionality in each cell. A simple, high-speed busing

network provides fast, efficient communication over medium and long distances.

AT40KAL Series FPGA [Datasheet]

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Atmel-2818G-FPGA-AT40KAL-Series-Datasheet_092013

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