AT80C51RD2-SLSUL View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

AT80C51RD2-SLSUL

80C51 High Performance ROM 8-bit Microcontroller

Atmel Corporation 

Table 5. CKCON0 Register

CKCON0 - Clock Control Register (8Fh)

7

6

5

4

3

2

1

0

-

WDX2

PCAX2

SIX2

T2X2

T1X2

T0X2

X2

Bit

Number

7

6

5

4

3

2

1

0

Bit

Mnemonic

-

WDX2

PCAX2

SIX2

T2X2

T1X2

T0X2

X2

Description

Reserved

Do not set this bit.

Watchdog clock (This control bit is validated when the CPU clock X2 is set;

when X2 is low, this bit has no effect).

Cleared to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

Programmable Counter Array clock (This control bit is validated when the

CPU clock X2 is set; when X2 is low, this bit has no effect).

Cleared to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

Enhanced UART clock (Mode 0 and 2) (This control bit is validated when the

CPU clock X2 is set; when X2 is low, this bit has no effect).

Cleared to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

Timer 2 clock (This control bit is validated when the CPU clock X2 is set; when

X2 is low, this bit has no effect).

Cleared to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

Timer 1 clock (This control bit is validated when the CPU clock X2 is set; when

X2 is low, this bit has no effect).

Cleared to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle

Timer 0 clock (This control bit is validated when the CPU clock X2 is set; when

X2 is low, this bit has no effect).

Cleared to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle

CPU clock

Cleared to select 12 clock periods per machine cycle (STD mode) for CPU and

all the peripherals.

Set to select 6clock periods per machine cycle (X2 mode) and to enable the

individual peripherals "X2" bits.

Programmed by hardware after Power-up regarding Hardware Config Byte

(HCB).

Reset Value = 0000 000’HCB.X2’b (see Hardware Config Byte)

Not bit addressable

12 AT80C51RD2/AT83C51Rx2

4113B–8051–03/05

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