XRD9812 View Datasheet(PDF) - Exar Corporation
Part Name
Description
Manufacturer
XRD9812 Datasheet PDF : 32 Pages
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XRD9810/12
PGA Gain Settings
The gain for each color input is individually programmable
from 1 to 10 in 256 linear steps.
PGA
Gain
=
æ
è
Code
256
öø×9.0
+
1.0
where Code represents the decimal contents of the binary
8-bit gain setting register.
Channel Offset Adjustment
The offset correction for each channel is programmable
from -300mV to +300mV via an 8-Bit sign-magnitude Dac.
Channel Offset = PB7 . éëê (C1o2d8e)ùûú×300mV
PB7=1 equals -1
PB7=0 equals +1
Code = (PB6:PB0) decimal content of the binary 8-bit
offset register.
Theory of Operation (Correlated Double Sampling)
Correlated double sampling is a technique used to level
shift and acquire CCD output signals whose information is
equal to the difference between consecutive reference
(black) and signal (video) samples. The CDS process
consists of three steps.
1) Sampling and holding the reference black level.
2) Sampling the video level.
3) Subtracting the two samples to extract the video
information.
Once the video information has been extracted it can be
processed further through amplification and/or offset
adjustment. Since system noise is also stored and
subtracted during the CDS process, signals with
bandwidths less than half the sampling frequency will be
substantially attenuated.
In order to reject higher frequency power supply noise
which is not attenuated near the sampling frequency the
XRD9810/12/20/22 utilizes a fully differential input
structure.
Since the CDS process uses AC coupled inputs the
coupling capacitor must be charged to the common-mode
range of the analog front-end. This can be accomplished
by clamping the coupling capacitor to the internal clamp
voltage when the CCD is at a reference level. This clamp
may occur during each pixel (Pixel Clamp), or at the
beginning of each line (CDS Line Clamp). If CDS Line
Clamp mode is used the input buffer (configuration
register #1, PB1) must be enabled to eliminate the effects
of input bias current. If Pixel mode is selected the input
buffer is not required or recommended.
3-Channel CDS Mode
This mode allows simultaneous CDS of the red, green
and blue inputs. Black-level sampling occurs on each
pixel and is equal to the width of the BSAMP sampling
input. The black level is held on the falling edge of BSAMP
and the PGA will immediately begin to track the signal
input until the falling edge of VSAMP.
Two VSAMP timing modes are supported to allow
additional flexibility in the VSAMP pulse width (see timing
diagrams). At the end of the video sampling phase the
difference between the reference and video levels is
inverted, amplified and offset depending on the contents
of the PGA gain and offset registers. The RGB channels
are then sequentially converted by a high speed A/D
converter. A/D converter data appears on the data
output bus after ADCCLK cycles.
Channel
synchronization occurs when the rising edge of ADCCLK
samples a logic 0 on the SYNCH input. The Red channel
is always digitized first following synchronization and will
be selected as long as the rising edge of ADCCLK
samples a logic 0 on the SYNCH input. The power up
default mode is for CDS sampling a CCD input (Pixel
Clamp, Inverting input, no input buffer).
1-Channel CDS Mode
The 1-channel CDS mode allows high-speed acquisition
and processing of a single channel. The timing, clamp
and buffer configurations are similar to the 3-channel
mode describe previously. To select a single channel
input the color bits of Configuration Register #1 must be
set to the appropriate value. The A/D input will begin to
track the selected color input on the next positive edge of
ADCCLK. In single color mode the SYNCH signal has no
effect on synchronization but still affects clamping. (See
Table 1). If the configuration is toggled from single color to
3-channel mode RGB scanning will not occur until the
circuit is resynchronized with the SYNCH pulse.
Rev. 1.00
18
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