C8051F300 View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

C8051F300

Mixed Signal ISP Flash MCU Family

Unspecified 

C8051F300/1/2/3/4/5

DOCUMENT CHANGE LIST

Revision 2.3 to Revision 2.4

• Removed preliminary tag.

• Changed all references of MLP package to QFN package.

• Pinout chapter: Figure 4.3: Changed title to “Typical QFN-11 Solder Paste Mask.”

• ADC chapter: Added reference to minimum tracking time in the Tracking Modes section.

• Comparators chapter: SFR Definition 7.3, CPT0MD: Updated the register reset value and the CP0

response time table.

• CIP51 chapter: Updated IDLE mode and recommendations.

• CIP51 chapter: Updated Interrupt behavior and EA recommendations.

• CIP51 chapter: SFR Defintion 8.4, PSW: Clarified OV flag description.

• CIP51 chapter: SFR Defintion 8.8, IP register: Changed “default priority order” to “low priority” for low

priority descriptions.

• Reset Sources chapter: Clarified description of VDD Ramp Time.

• Reset Sources chapter: Table 9.2, “Reset Electrical Characteristics”: Added VDD Ramp Time and

changed “VDD POR Threshold” to “VDD Monitor Threshold.”

• FLASH Memory chapter: Clarified descriptions of FLASH security features.

• Oscillators chapter: Table 11.1 “Internal Oscillator Electrical Characteristics”: Added Calibrated Internal

Oscillator specification over a smaller temperature range.

• Oscillators chapter: Clarified external crystal initialization steps and added a specific 32.768 kHz crys-

tal example.

• Oscillators chapter: Clarified external capacitor example.

• SMBus chapter: Figure 14.5, SMB0CF register: Added a description of the behavior of Timer 3 in split

mode if SMBTOE is set.

• Timers chapter: Changed references to “TL2” and “TH2” to “TMR2L” and “TMR2H,” respectively.

Revision 2.4 to Revision 2.5

• Fixed variables and applied formatting changes.

Revision 2.5 to Revision 2.6

• Updated Table 1.1 Product Selection Guide to include Lead-free information.

172

Rev. 2.6

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