LRCK
t slrd
SCLK
SDATA
t sdlrs
t slrs
t sclkh
t sclkl
t sdh
Figure 1. External Serial Mode Input Timing
LRCK
SDATA
*INTERNAL SCLK
t sclkr
t sdlrs t sdh
t sclkw
Figure 2. Internal Serial Mode Input Timing
*The SCLK pulses shown are internal to the CS4340.
LRCK
MCLK
1
N
N
2
*INTERNAL SCLK
DS297PP3
SDATA
Figure 3. Internal Serial Clock Generation
* The SCLK pulses shown are internal to the CS4340.
N equals MCLK divided by SCLK
CS4340
11