CS5550
pulse-low, the duration of the INT pulse will be at
least one DCLK cycle (DCLK = MCLK / K).
3.6 PCB Layout
The CS5550 should be placed entirely over an an-
alog ground plane with both the AGND and DGND
pins of the device connected to the analog plane.
Place the analog-digital plane split immediately ad-
jacent to the digital portion of the chip.
14
DS630F1