CX28331-3X View Datasheet(PDF) - Conexant Systems
Part Name
Description
Manufacturer
CX28331-3X Datasheet PDF : 68 Pages
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1.0 Pin Description
1.1 Pin Assignments
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
Table 1-1. CX2833i-1x Pin Definitions (6 of 6)
Pin #
Signal Name
CX28331-1x CX28332-1x CX28333-1x
Description
I/O/P
Notes
4, 5, 20, 21 12, 13
—
1, 8, 17, 24
9, 16
—
VDD Power
VSS Ground
P Connect to 3.3 V power.
P Connect to ground.
Miscellaneous
58
—
—
—
76
76
—
25
58
—
—
25
47
—
—
—
65
65
—
36
47
—
—
36
80
80
80
78
78
78
77
77
77
2, 3, 6, 7, 18, 10, 11, 14,
42
19, 22, 23, 15, 42,
25, 26, 27,
44–58
29, 30, 31,
32, 33, 34,
35, 36, 37,
38, 39, 40,
42, 61, 62,
63, 64, 65,
66, 67, 68,
69, 70, 71,
72, 74, 75,
76
PD
PD1
PD2
PD3
REFCLK
REFCLK1
REFCLK2
REFCLK3
RBIAS
Reset
GPD
NC
Power down for Ch1
Power down for Ch2
Power down for Ch3
Reference clock for Ch1
Reference clock for Ch2
Reference clock for Ch3
Bias resistor
Reset
Global Power down
No connect
I Power down transceiver channel
0 = Power down channel (off)
1 = Channel active (on)
I Note: A special power-down mode
exists when all three PDBs are set
I low. This special mode shuts off the
entire chip (including biasing). This
is useful for static Idd testing.
I Reference clock from off-chip.
This clock should be set to one of
the following:
I
• E3 rate (34.368 MHz)
• DS3 rate (44.736 MHz)
I
• STS-1 rate (51.84 MHz)
The clock rate should correspond to
the mode of operation that has been
chosen for the channel.
O A 12.1 kΩ ± 1% resistor tied from
this pin to ground provides the
current reference to the entire
chip.(2)
I/O Asynchronous reset (reset entire
device).
I/O Power down (Static Idd testing).
0 = Power down disable
1 = Power down active
— Not connected.
NOTE(S):
(1) This pin should be connected to 3.3 V in an all-3.3 V design.
(2) Placing a capacitor from this pin to ground may result in instabilities.
3. All digital input pins contain a 75 kΩ pull-down resistor from input to DVSS.
1-10
Conexant
100985A
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