CXP750096/750010, CXP750097/750011
Pin
Circuit format
Port F
SCL, SDA
I2C bus enable
∗
PF4/SCL0
PF5/SCL1/PWM4
PF6/SDA0
PF7/SDA1/PWM5
4 pins
PWM4, PWM5
Port F function selection
“0” after a reset
Port F data
“1” after a reset
Internal data bus
RD (Port F) Schmitt input
SCL, SDA
(I2C bus circuit)
∗ Large current 12mA
IP
BUS SW
To internal I2C pins
(SCL1 for SCL0)
After a reset
Hi-Z
R
G
B
3 pins
EXLC
XLC
R, G, B
Output polarity
“0” after a reset
Oscillation control
EXLC
IP
Writing data to output
polarity register brings
output to active.
Hi-Z
IP
OSD display clock
Oscillation
halted
2 pins
XLC
EXTAL
XTAL
2 pins
RST
1 pin
EXTAL
XTAL
IP
• Diagram shows the
circuit composition
during oscillation.
• Feedback resistor is
removed and XTAL is driven
at "H" level driving stop.
(This device does not enter the
stop mode.)
Pull-up resistor
OP Mask option
Schmitt input
– 11 –
Oscillation
Low level
(during a
reset)