CXP750096/750010, CXP750097/750011
Pin
PD0/INT2
PD3/SI
PD4/HS0
PD5/HS1
PD6/RMC
PD7/EC
6 pins
Port D
Circuit format
Port D data
After a reset
Port D direction
“0” after a reset
∗
Internal data bus
RD (Port D)
INT2, SI, HS0,
HS1, RMC, EC
Schmitt input IP
∗ Large current 12mA
Hi-Z
Port D
SCK, SO
SIO output enable
PD1/SCK
PD2/SO
2 pins
PE0/TO/ADJ
1 pin
Port D data
Port D direction
“0” after a reset
Internal data bus
RD (Port D)
SCK only
∗
IP
Schmitt input
only for PD1
∗ Large current 12mA
Port E
Internal reset signal
Port E data
00
“1” after a reset
ADJ16KT∗O1
01 MPX
10
∗2
ADJ2K∗1
11
Port E function selection (Upper)
Port E function selection (Lower)
“00” after a reset
Port E direction
“1” after a reset
Internal data bus
∗1 ADJ signals are frequency
dividing outputs for 32kHz
oscillation frequency
IP
adjustment. ADJ2K provides
usage as buzzer output.
∗2 Pull-up resistors approx. 150kΩ
RD (Port E)
Hi-Z
High level
( ) H level at ON
resistance of
pull-up
transistor
during a reset
–9–