CY7C1325G-133BGI View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY7C1325G-133BGI Datasheet PDF : 16 Pages
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CY7C1325G
Truth Table[2, 3, 4, 5, 6]
Cycle Description
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Sleep Mode, Power-down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Address
Used
None
None
None
None
None
None
External
External
External
External
External
Next
Next
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK
HXXL X
L
X
X
X L-H
L L XL
L
X
X
X
X L-H
L XHL
L
X
X
X
X L-H
L L XL H
L
X
X
X L-H
XXXL H
L
X
X
X L-H
X X XH X
L H LL
L
L H LL
L
LHLL H
LHLL H
LHLL H
XXXL H
XXXL H
HXXL X
HXXL X
XXXL H
HXXL X
XXXL H
XXXL H
HXXL X
HXXL X
XXXL H
HXXL X
X
X
X
XX
X
X
X
L L-H
X
X
X
H L-H
L
X
L
X L-H
L
X
H
L L-H
L
X
H
H L-H
H
L
H
L L-H
H
L
H
H L-H
H
L
H
L L-H
H
L
H
H L-H
H
L
L
X L-H
H
L
L
X L-H
H
H
H
L L-H
H
H
H
H L-H
H
H
H
L L-H
H
H
H
H L-H
H
H
L
X L-H
H
H
L
X L-H
DQ
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
Q
Tri-State
D
Q
Tri-State
Q
Tri-State
Q
Tri-State
D
D
Q
Tri-State
Q
Tri-State
D
D
Truth Table for Read/Write[2]
Function
Read
Read
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
Write All Bytes
Write All Bytes
GW
BWE
BWB
BWA
H
H
X
X
H
L
H
H
H
L
H
L
H
L
L
H
H
L
L
L
L
X
X
X
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write enable signals (BWA, BWB) and BWE = L or GW = L. WRITE = H when all Byte write enable signals (BWA, BWB),
BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A: B]. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a
don't care for the remainder of the write cycle.
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05518 Rev. *D
Page 6 of 16
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