AD8109ASTZ(2016) View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD8109ASTZ
(Rev.:2016)

325 MHz, 8 × 8 Buffered Video Crosspoint Switches

Analog Devices 

AD8108/AD8109

TIMING CHARACTERISTICS (PARALLEL)

Table 4. Timing Characteristics

Parameter

Data Setup Time

CLK Pulse Width

Data Hold Time

CLK Pulse Separation

CLK to UPDATE Delay

UPDATE Pulse Width

Propagation Delay, UPDATE to Switch On or Off

CLK, UPDATE Rise and Fall Times

RESET Time

Data Sheet

Symbol

t1

t2

t3

t4

t5

t6

–

–

–

Min

Typ

Max

Unit

20

ns

100

ns

20

ns

100

ns

0

ns

50

ns

8

ns

100

ns

200

ns

Table 5. Logic Levels

VIH

VIL

RESET, SER/PAR

CLK, D0, D1, D2,

D3, A0, A1, A2

CE, UPDATE

RESET, SER/PAR

CLK, D0, D1, D2,

D3, A0, A1, A2

CE, UPDATE

2.0 V min

0.8 V max

VOH

DATA OUT

2.7 V min

VOL

DATA OUT

0.5 V max

IIH

RESET, SER/PAR

CLK, D0, D1, D2,

D3, A0, A1, A2

CE, UPDATE

20 µA max

IIL

RESET SER/PAR

CLK, D0, D1, D2,

D3, A0, A1, A2

CE, UPDATE

−400 µA min

IOH

DATA OUT

−400 µA max

IOL

DATA OUT

3.0 mA min

1

CLK

0

1

D0–D3

A0–A2

0

1 = LATCHED

UPDATE

0 = TRANSPARENT

t2

t4

t1

t3

Figure 3. Timing Diagram, Parallel Mode

t5 t6

Rev. C | Page 6 of 27

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