CY8C20111(2009) View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY8C20111
(Rev.:2009)
(Rev.:2009)
Cypress Semiconductor
CY8C20111 Datasheet PDF : 34 Pages
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PRELIMINARY
CY8C20111, CY8C20121
7.1 OUTPUT_PORT
Output Port Register
OUTPUT_PORT: 04h
1 Button
7
6
5
4
3
2
1
0
Access: FD
W:01
Bit Name
DIG[0]
2 Button
7
6
5
4
3
2
1
0
Access: FD
W:03
Bit Name
DIG[1:0]
This register is used to write data to DIG output port. Pins defined as output of combinational logic (in OP_SEL_x register) cannot be
changed using this register.
Bit
Name
1:0
DIG [1:0]
Description
A bit set in this register sets the logic level of the output.
0
Logic ‘0’
1
Logic ‘1’
7.2 CS_ENABLE
Select CapSense Input Register
CS_ENABLE: 07h
(Writable only in Setup mode)
1 Button
7
6
5
4
3
2
1
0
Access: FD
RW:01
Bit Name
CS[0]
2 Button
7
6
5
4
3
2
1
0
Access: FD
RW:03
Bit Name
CS[1:0]
This register is used to enable CapSense inputs. This register should be set before setting finger threshold (0x66, 0x67) and
IDAC setting (0x70, 0x71) registers.
Bit
Name
1:0
CS [1:0]
Description
These bits are used to enable CapSense inputs.
0
Disable CapSense input
1
Enable CapSense input
Document Number: 001-53516 Rev. **
Page 9 of 34
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