CY8C20121 View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY8C20121
Cypress Semiconductor
CY8C20121 Datasheet PDF : 34 Pages
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CY8C20111, CY8C20121
Operating Modes
Normal Mode
In normal mode of operation, the acknowledgment time is
optimized. The timings remain approximately the same for
different configurations of the slave. To reduce the
acknowledgment times in normal mode, the registers 0x07,
0x08, 0x11, 0x50, 0x51, 0x5C, 0x5D are given only read access.
Writing to these registers can be done only in setup mode.
Setup Mode
All registers have read and write access (except those which are
read only) in this mode. The acknowledgment times are longer
compared to normal mode. When CapSense scanning is
disabled (command code 0x0A in command register 0xA0), the
acknowledgment times can be improved to values similar to the
normal mode of operation.
I2C Interface
The CapSense Express devices support the industry standard
I2C protocol, which can be used to:
â– Configure the device
â– Read the status and data registers of the device
â– Control device operation
â– Execute commands
The I2C address can be modified during configuration.
I2C Device Addressing
The device uses a seven bit addressing protocol. The I2C data
transfer is always initiated by the master sending one byte
address; first 7-bit contains address and LSb indicates the data
transfer direction. Zero in the LSb indicates the write transaction
form master and one indicates read transfer by the master.
Table 3 shows example for different I2C addresses.
Table 1. I2C Addresses
7-bit Slave Address (in
Dec)
D7
D6
D5
D4
D3
D2
D1
D0
8-bit Slave Address (in
Hex)
1
0
0
0
0
0
0
1
0(W)
02
1
0
0
0
0
0
0
1
1(R)
03
75
1
0
0
1
0
1
1
0(W)
96
75
1
0
0
1
0
1
1
1(W)
97
I2C Clock Stretching
“Clock stretching†or “bus stalling†in I2C communication protocol
is a state in which the slave holds the SCL line low to indicate
that it is busy. In this condition, the master is expected to wait
until the SCL is released by the slave.
When an I2C master communicates with the CapSense Express
device, the CapSense Express stalls the I2C bus after the
reception of each byte (that is, just before the ACK/NAK bit) until
processing of the byte is complete and critical internal functions
are executed. Use a fully I2C compliant master to communicate
with the CapSense Express device.
An I2C master which does not support clock stretching (a bit
banged software I2C Master) must wait for a specific amount of
time specified (as shown in the section Format for Register Write
and Read) for each register write and read operation before the
next bit is transmitted. It is mandatory to check the SCL status (it
should be high) before I2C master initiates any data transfer with
CapSense Express. If the master fails to do so and continues to
communicate, the communication is erroneous.
The following diagrams represent the ACK time delays shown in
the Register Map on page 7.
Figure 8. Write ACK Time Representation
Document Number: 001-53516 Rev. *H
Page 8 of 44
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