MT48LC128M4A2P View Datasheet(PDF) - Micron Technology

Part Name

Description

Manufacturer

MT48LC128M4A2P

Synchronous DRAM

Micron Technology 

512Mb: x4, x8, x16 SDRAM

Operations

The procedure for exiting self refresh requires a sequence of commands. First, CLK must

be stable (stable clock is defined as a signal cycling within timing constraints specified

for the clock pin) prior to CKE going back HIGH. When CKE is HIGH, the SDRAM must

have NOP commands issued (a minimum of two clocks) for tXSR because time is

required for the completion of any internal refresh in progress.

Upon exiting the self refresh mode, AUTO REFRESH commands must be issued every

7.81µs or less as both SELF REFRESH and AUTO REFRESH utilize the row refresh

counter.

Operations

Bank/Row Activation

Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row

in that bank must be “opened.” This is accomplished via the ACTIVE command, which

selects both the bank and the row to be activated (see Figure 7).

After opening a row (issuing an ACTIVE command), a READ or WRITE command may be

issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by

the clock period and rounded up to the next whole number to determine the earliest

clock edge after the ACTIVE command on which a READ or WRITE command can be

entered. For example, a tRCD specification of 20ns with a 125 MHz clock (8ns period)

results in 2.5 clocks, rounded to 3. This is reflected in Figure 8 on page 21, which covers

any case where 2 < tRCD (MIN)/tCK ≤ 3 (the same procedure is used to convert other

specification limits from time units to clock cycles). A subsequent ACTIVE command to

a different row in the same bank can only be issued after the previous active row has

been “closed” (precharged). The minimum time interval between successive ACTIVE

commands to the same bank is defined by tRC.

Figure 7: Activating a Specific Row In a Specific Bank

CLK

CKE HIGH

CS#

RAS#

CAS#

WE#

A0–A12

ROW

ADDRESS

BA0, BA1

PDF: 09005aef809bf8f3/Source: 09005aef80818a4a

512MbSDRAM.fm - Rev. L 10/07 EN

BANK

ADDRESS

Don’t Care

20

Micron Technology, Inc., reserves the right to change products or specifications without notice.

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