WS256K32-XXX
FIG. 4
TIMING WAVEFORM - READ CYCLE
ADDRESS
DATA I/O
tRC
tAA
tOH
PREVIOUS DATA VALID
DATA VALID
READ CYCLE 1 (CS = OE = VIL, WE = VIH)
ADDRESS
CS
OE
DATA I/O
tRC
tAA
tACS
tCLZ
tCHZ
tOE
tOLZ
HIGH IMPEDANCE
tOHZ
DATA VALID
READ CYCLE 2 (WE = VIH)
FIG. 5
WRITE CYCLE - WE CONTROLLED
ADDRESS
CS
WE
DATA I/O
tWC
tAW
tCW
tAH
tAS
tWP
tWHZ
tOW
tDW
tDH
DATA VALID
WRITE CYCLE 1, WE CONTROLLED
FIG. 6
WRITE CYCLE - CS CONTROLLED
ADDRESS
tAS
CS
tWC
WS32K32-XHX
tAW
tCW
tAH
WE
DATA I/O
tWP
tDW
tDH
DATA VALID
WRITE CYCLE 2, CS CONTROLLED
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com