DS2726G(2008) View Datasheet(PDF) - Maxim Integrated
Part Name
Description
Manufacturer
DS2726G Datasheet PDF : 15 Pages
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5- to 10-Cell Li+ Protector with Cell Balancing
PIN
1
2
3
4, 5
6
7
8
9
10, 11
12, 13
14, 30
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Pin Description
NAME
RSC
RDOC
VCC
SEL0,
SEL1
CDOCD
SLEEP
CSCD
CBCFG
CBS0,
CBS1
OVS0,
OVS1
N.C.
GND
V00
V01
V02
V03
V04
V05
V06
V07
V08
V09
V10
VIN
DC
FUNCTION
Short-Circuit Voltage Threshold. The resistor from this pin to the positive terminal of the cell stack
selects the threshold voltage for a short-circuit condition in the discharge direction.
Discharge Overcurrent Voltage Threshold. The resistor from this pin to the positive terminal of the cell
stack selects the threshold voltage for an overcurrent condition in the discharge direction.
Regulator Supply Output. VCC supplies power to internal circuits and can be used to pull configuration
pins to VIH. It should be bypassed to GND with at least a 0.1μF ceramic capacitor.
Select Number of Cells in the Battery Stack. This input is a three-level input. Connect to ground or VCC
for a logic-low or logic-high, respectively. Leave unconnected to achieve the midthreshold. See Table
2 for how to drive this pin for a particular number of cells.
Discharge Overcurrent Delay Time. Connect a capacitor from this pin to GND to select the amount of
time for which a discharge overcurrent condition must persist before shutting off the DC FET.
Sleep-Mode Select Input. Driving this pin to a logic-low level forces the part into the lowest power state.
The part exits Sleep Mode once a charge voltage is applied. When CBCFG is high, a logic-high on this
pin enables cell balancing.
Short-Circuit Current Delay Time. Connect a capacitor from this pin to GND to select the amount of time
for which a short-circuit current condition must persist before shutting off the DC FET.
Charge-Balance Configuration Input. When this pin is at a logic-low, charge balancing is enabled if
VPKP > VVIN + VCDET. When this pin is at a logic-high, charge balancing is enabled if the SLEEP pin is
at a logic-high.
Select Cell-Balancing Voltage. This input is a three-level input. Connect to ground or VCC for a logic-low
or logic-high, respectively. Leave unconnected to achieve the midthreshold. See Table 4 for how to
drive this pin for a particular cell-balancing voltage threshold.
Select Overvoltage Threshold. This input is a three-level input. Connect to ground or VCC for a logic-low
or logic-high, respectively. Leave unconnected to achieve the midthreshold. See Table 3 for how to
drive this pin for a particular overvoltage threshold.
No Connection. Not internally connected.
Ground. Connect to the negative terminal of the lowest voltage cell.
Negative Terminal Voltage Sense. Connect to the negative terminal of the 1st cell in the battery stack.
Cell 01 Voltage Sense. Connect to the positive terminal of the 1st cell in the battery stack.
Cell 02 Voltage Sense. Connect to the positive terminal of the 2nd cell in the battery stack.
Cell 03 Voltage Sense. Connect to the positive terminal of the 3rd cell inf the battery stack.
Cell 04 Voltage Sense. Connect to the positive terminal of the 4th cell in the battery stack.
Cell 05 Voltage Sense. Connect to the positive terminal of the 5th cell in the battery stack.
Cell 06 Voltage Sense. Connect to the positive terminal of the 6th cell in the battery stack.
Cell 07 Voltage Sense. Connect to the positive terminal of the 7th cell in the battery stack.
Cell 08 Voltage Sense. Connect to the positive terminal of the 8th cell in the battery stack.
Cell 09 Voltage Sense. Connect to the positive terminal of the 9th cell in the battery stack.
Cell 10 Voltage Sense. Connect to the positive terminal of the 10th cell in the battery stack.
Connect to the Most Positive Cell Terminal
Discharge Control Output. DC controls the gate of the discharge FET. Driven from VIN to VOLDC to turn
on and turn off the discharge FET.
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