DSP56303 View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

DSP56303

DSP56303 24-bit digital signal processor (DSP)

Freescale Semiconductor 

1.5 DSP56300 Core

DSP56300 Core

Core features are fully described in the DSP56300 Family Manual. This manual, in contrast,

documents pinout, memory, and peripheral features. Core features are as follows:

„ 100 million instructions per second (MIPS) with a 100 MHz clock at 3.0–3.6 V

„ Highly parallel instruction set

„ Data arithmetic logic unit (Data ALU)

— Fully pipelined 24 × 24-bit parallel multiplier-accumulator (MAC)

— 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and

parsing)

— Conditional ALU instructions

— 24-bit or 16-bit arithmetic support under software control

„ Program control unit (PCU)

— Position Independent Code (PIC) support

— Addressing modes optimized for DSP applications (including immediate offsets)

— Instruction cache controller

— Internal memory-expandable hardware stack

— Nested hardware DO loops

— Fast auto-return interrupts

„ Direct memory access (DMA)

— Six DMA channels supporting internal and external accesses

— One-, two-, and three- dimensional transfers (including circular buffering)

— End-of-block-transfer interrupts

— Triggering from interrupt lines and all peripherals

„ Phase lock loop (PLL)

— Allows change of low power Divide Factor (DF) without loss of lock

— Output clock with skew elimination

„ Hardware debugging support

— On-chip emulation (OnCE) module

— Joint Test Action Group (JTAG) Test Access Port (TAP)

— Address Trace mode reflects internal program RAM accesses at the external port

„ Reduced power dissipation

— Very low-power CMOS design

— Wait and stop low-power standby modes

— Fully-static design specified to operate down to 0 Hz (dc)

— Optimized power-management circuitry (instruction-dependent, peripheral-dependent,

and mode-dependent)

DSP56303 User’s Manual, Rev. 2

Freescale Semiconductor

1-5

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