EL5411IRE-T7 View Datasheet(PDF) - Intersil
Part Name
Description
Manufacturer
EL5411IRE-T7 Datasheet PDF : 18 Pages
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EL5111, EL5211, EL5411
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the loads, or:
PDMAX = Σi[VS × ISMAX + (VS+ – VOUTi ) × ILOADi ]
(EQ. 2)
when sourcing, and:
PDMAX = Σi[VS × ISMAX + (VOUTi – VS- ) × ILOADi ]
(EQ. 3)
when sinking,
where:
• i = 1 to 2 for dual and 1 to 4 for quad
• VS = Total supply voltage
• ISMAX = Maximum supply current per amplifier
• VOUTi = Maximum output voltage of the application
• ILOADi = Load current
If we set the two PDMAX equations equal to each other, we
can solve for RLOADi to avoid device overheat. Figures 29-
36 provide a convenient way to see if the device will
overheat. The maximum safe power dissipation can be
found graphically, based on the package type and the
ambient temperature. By using the previous equation, it is a
simple matter to see if PDMAX exceeds the device's power
derating curves. To ensure proper operation, it is important
to observe the recommended derating curves shown in
Figures 29-36.
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
0.9
0.8
694mW
0.7
0.6
HTSSOP14
θJA=+144°C/W
0.5
0.4
0.3
0.2
0.1
0.0
0
25
50
75 85 100
125
AMBIENT TEMPERATURE (°C)
FIGURE 29. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY (4-LAYER) TEST BOARD -
HTSSOP EXPOSED DIEPAD SOLDERED TO
PCB PER JESD51-5
3.5
3.0
2.632W
2.5
2.0
HTSSOP14
θJA=+38°C/W
1.5
1.0
0.5
0.0
0
25
50
75 85 100
125
AMBIENT TEMPERATURE (°C)
FIGURE 30. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.2
TSSOP28
1.0
0.8
1.042W
0.6
977mW
0.4 893mW
845mW
0.2
758mW
0.0
0
25
50
θJA=+120°C/W
TSSOP24
θJA=+128°C/W
TSSOP20
θJA=+140°C/W
TSSOP16
θJA=+148°C/W
TSSOP14
θJA=+165°C/W
75 85 100 125 150
AMBIENT TEMPERATURE (°C)
FIGURE 31. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.8
TSSOP28
1.6
θJA=+75°C/W
1.4
TSSOP24
1.2
1.0 1.667W
θJA=+85°C/W
TSSOP20
0.8 1.471W
θJA=+90°C/W
0.6 1.389W
TSSOP16
0.4 1.289W
θJA=+97°C/W
0.2 1.250W
0.0
TSSOP14
θJA=+100°C/W
0
25
50
75 85 100 125 150
AMBIENT TEMPERATURE (°C)
FIGURE 32. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
12
FN7119.5
January 10, 2007
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