EtronTech
EM636327
Electrical Characteristics and Recommended A.C. Operating Conditions
(VDD = 3.3V¡Ó0.3V, Ta = 0~70°C) (Note: 5, 6, 7, 8)
Symbol
A.C. Parameter
tRC Row cycle time
(same bank)
tRCD RAS# to CAS# delay
(same bank)
tRP Precharge to refresh/row activate command
(same bank)
tRRD Row activate to row activate delay
(different banks)
tRAS Row activate to precharge time
(same bank)
tWR Write recovery time
tCK1
CL* = 1
tCK2 Clock cycle time
CL* = 2
tCK3
CL* = 3
tCH Clock high time
tCL
Clock low time
tAC1 Access time from CLK
CL* = 1
tAC2 (positive edge)
CL* = 2
tAC3
CL* = 3
tCCD CAS# to CAS# Delay time
tOH Data output hold time
tLZ
Data output low impedance
tHZ Data output high impedance
tIS
Data/Address/Control Input set-up time
tIH
Data/Address/Control Input hold time
tSRX Minimum CKE "High" for SelfRefresh exit
tPDE PowerDown Exit set-up time
tRSC (Special) Mode Register Set Cycle time
tBWC Block Write Cycle time
tBPL Block Write to Precharge command period
tREF Refresh time
- 55/6/7/8/10
Min.
Max.
Unit
48/54/63/72/90
16/16/16/16/30
16/16/16/16/30
11/12/14/16/20
32/36/42/48/60
100,000
5.5/6/7/8/10
19/20/20/20/30
7/7.5/8/8/15
5.5/6/7/8/10
2/2/2.5/3/3.5
2/2/2.5/3/3.5
1
2/2/2/2/3
1/1/1/2/2
2/2/2/2.5/3
1
5.5/6/7/8/10
3.5/4/5/6/8
5.5/6/7/8/10
11/12/14/16/20
11/12/14/16/20
ns
7/8/13/18/27
5.5/6/6.5/7/12
5/5/5.5/6.5/7.5
Cycle
3.5/4/5/6/8
ns
32
ms
Note
9
9
9
9
10
11
11
11
10
8
11
11
11
9
* CL is CAS# Latency.
Preliminary
21
December 1998