EVAL-AD7656-1EDZ View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
EVAL-AD7656-1EDZ
Analog Devices
EVAL-AD7656-1EDZ Datasheet PDF : 32 Pages
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AD7656-1/AD7657-1/AD7658-1
TIMING SPECIFICATIONS
AVCC/DVCC = 4.75 V to 5.25 V, VDD = 5 V to 16.5 V, VSS = −5 V to −16.5 V, VDRIVE = 2.7 V to 5.25 V, VREF = 2.5 V internal/external,
TA = TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter1
PARALLEL INTERFACE
tCONVERT
tQUIET
tACQ
t10
t1
tWAKE-UP
PARALLEL WRITE OPERATION
t11
t12
t13
t14
t15
PARALLEL READ OPERATION
t2
t3
t4
t5
t6
t7
t8
t9
SERIAL INTERFACE
fSCLK
t16
t17 2
t18
t19
t20
t21
Limit at tMIN, tMAX
VDRIVE < 4.75 V VDRIVE = 4.75 V to 5.25 V
Unit
Description
3
3
150
150
550
550
25
25
60
60
2
2
25
25
μs typ
ns min
ns min
ns min
ns min
ms max
μs max
Conversion time, internal clock
Minimum quiet time required between bus
relinquish and start of next conversion
Acquisition time
Minimum CONVST low pulse
CONVST high to BUSY high
STBY rising edge to CONVST rising edge
Partial power-down mode
15
15
0
0
5
5
5
5
5
5
ns min
ns min
ns min
ns min
ns min
WR pulse width
CS to WR setup time
CS to WR hold time
Data setup time before WR rising edge
Data hold after WR rising edge
0
0
0
0
0
0
45
36
45
36
10
10
12
12
6
6
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
BUSY to RD delay
CS to RD setup time
CS to RD hold time
RD pulse width
Data access time after RD falling edge
Data hold time after RD rising edge
Bus relinquish time after RD rising edge
Minimum time between reads
18
12
22
0.4 × tSCLK
0.4 × tSCLK
10
18
18
12
22
0.4 × tSCLK
0.4 × tSCLK
10
18
MHz max
ns max
ns max
ns min
ns min
ns min
ns max
Frequency of serial read clock
Delay from CS until DOUTx three-state
disabled
Data access time after SCLK rising edge/CS
falling edge
SCLK low pulse width
SCLK high pulse width
SCLK to data valid hold time after SCLK
falling edge
CS rising edge to DOUTx high impedance
1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
2 A buffer is used on the DOUTx pins (Pin 5 to Pin 7) for this measurement.
200µA
IOL
TO OUTPUT
PIN CL
25pF
1.6V
200µA
IOH
Figure 2. Load Circuit for Digital Output Timing Specifications
Rev. 0 | Page 9 of 32
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