FAN6756 View Datasheet(PDF) - Fairchild Semiconductor

Part Name

Description

Manufacturer

FAN6756

mWSaver™ PWM Controller

Fairchild Semiconductor 

Functional Description

Current Mode Control

FAN6756 employs Peak-Current Mode control, as

shown in Figure 27. An opto-coupler (such as the

H11A817A) and a shunt regulator (such as the KA431)

are typically used to implement the feedback network.

Comparing the feedback voltage with the voltage

across the Rsense resistor makes it possible to control

the switching duty cycle. The built-in slope

compensation stabilizes the current loop and prevents

sub-harmonic oscillation.

fS

fOSC

fOSC-G

VFB-ZDC1 VFB-ZDCR1 VFB-G

VFB-N

VFB

Figure 28. VFB vs. PWM Frequency

Figure 27. Current-Mode Control Circuit Diagram

Leading-Edge Blanking (LEB)

Each time the power MOSFET is switched on, a turn-on

spike occurs on the sense resistor. To avoid premature

termination of the switching pulse, a leading-edge

blanking time, tLEB, is introduced. During this blanking

period, the current-limit comparator is disabled and

cannot switch off the gate driver.

mWSaver™ Technology

Green-Mode

FAN6756 modulates the PWM frequency as a function

of the FB voltage to improve the medium- and light-load

efficiency, as shown in Figure 28. Since the output

power is proportional to the FB voltage in Current-Mode

control, the switching frequency decreases as load

decreases. In heavy-load conditions, the switching

frequency is fixed at 65 kHz. Once VFB decreases below

VFB-N (2.8 V), the PWM frequency starts linearly

decreasing from 65 kHz to 23 kHz to reduce switching

losses. As VFB drops to VFB-G (2.3 V), where switching

frequency is decreased to 23 kHz, the switching

frequency is fixed to avoid acoustic noise.

When VFB falls below VFB-ZDC (2.0 V) as load decreases

further, the FAN6756 enters Burst Mode, where PWM

switching is disabled. Then the output voltage starts to

drop, causing the feedback voltage to rise. Once VFB

rises above VFB-ZDCR (2.1 V), switching resumes. Burst

Mode alternately enables and disables switching,

thereby reducing switching loss for lower power

consumption, as shown in Figure 29.

Figure 29. Burst Switching in Green Mode

Deep Burst Mode & Feedback Impedance Switching

Deep Burst Mode is defined as a special operational

mode to minimize power consumption at extremely light-

load or no-load condition where, not only the switching

loss, but also power consumption of the FAN6756 itself,

are reduced further than in Green Mode. Deep Burst

Mode is initiated when the non-switching state of burst

switching in Green Mode persists longer than tDBM

(7.5 ms) for three consecutive burst switchings (as

shown in Figure 30). To prevent entering Deep Burst

Mode during dynamic load change, there is tD-DBM

(>600 ms) delay. If there are more than 112 consecutive

switching pulses during the tD-DBM delay, the FAN6756

does not go into Deep Burst Mode.

Once the FAN6756 enters Deep Burst Mode, the

feedback impedance, ZFB, is modulated by the

impedance modulator, as shown in Figure 31. When VFB

is under a threshold level, the impedance modulator

clamps VFB and disables switching. When VDD drops to

VDD-ZFBR (7 V, which is 0.5 V higher than VUVLO), the

impedance modulator controls ZFB, allowing VFB to rise

and resume switching operation. As shown in Figure 32,

by clamping VFB to disable switching while modulating

ZFB to enable switching, the system is forced into a

“Deep” Burst Mode to reduce switching loss.

Deep Burst Mode maintains VDD as low as possible so

power consumption can be minimized. When the

FAN6756 enters Deep Burst Mode, several blocks are

disabled and the operation current is reduced from

IDD-OP1 (1.8 mA) to IDD-OP2 (450 µA).

© 2011 Fairchild Semiconductor Corporation

FAN6756 • Rev. 2.0.0

12

www.fairchildsemi.com

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